Airgap Spacer Reduces Parasitic Capacitance in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, parasitic capacitance between conductors increases as device dimensions shrink, leading to issues like RC delay, power dissipation, and cross-talk, which existing technologies struggle to mitigate effectively, especially between gates and contacts or interconnects.
Innovation Solution
The method involves forming air spacers by creating a sacrificial region between the gate and contact, recessing it, and depositing a dielectric material to trap air pockets, reducing parasitic capacitance by using a multi-layer spacer structure with divots and plugs to encase the sacrificial layer and form voids, which are then filled with dielectric material to create airgaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration density, then productivity and integration density are improved, but parasitic capacitance between conductors increases leading to RC delay and power dissipation
Solution Approach 1:
The patent extracts the harmful dielectric material from the region between the gate electrode and contact, replacing it with an air gap (vacuum/air space). This removal of the solid dielectric eliminates the parasitic capacitance pathway while maintaining the necessary electrical isolation, directly addressing the energy loss problem caused by device scaling.
Solution Approach 2:
The patent changes the dielectric parameter (permittivity) of the spacer region from a high-k material to air/vacuum (k≈1). This parameter change dramatically reduces the capacitance value between gate and contact, thereby reducing RC delay and power dissipation while allowing continued device miniaturization.
2Loss of energy
If airgap is formed between gate and contact to reduce parasitic capacitance, then parasitic capacitance and RC delay are reduced, but manufacturing complexity increases due to multi-layer spacer structure with divots and plugs
Solution Approach 1:
The patent performs preliminary actions by forming the multi-layer spacer structure with divots and plugs before final contact formation. The sacrificial layer is patterned with divots and filled with plugs in advance, creating a template that guides subsequent airgap formation. This preliminary structuring simplifies the overall process by pre-defining where the airgap should form.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary material that facilitates airgap formation. This sacrificial layer is deposited, patterned with divots, and filled with plugs to create a temporary structure that defines the airgap region. After the airgap is formed, the sacrificial material is removed, leaving the desired air space between gate and contact.
3Loss of energy
If airgap spacer is formed to reduce parasitic capacitance, then power dissipation is reduced, but gate current leakage may occur without proper encasement of sacrificial layer
Solution Approach 1:
The patent uses a nested structure where the sacrificial layer is completely encased within the multi-layer spacer system. The divots in the sacrificial layer are filled with plugs, and the entire sacrificial structure is surrounded by spacer layers. This nested arrangement ensures that when the sacrificial material is removed, no residual material remains to cause gate current leakage, while the airgap provides the desired electrical isolation.
Solution Approach 2:
The patent performs preliminary encasement of the sacrificial layer with the multi-layer spacer structure before airgap formation. The divots are created and filled with plugs in advance, creating a sealed environment around the sacrificial material. This preliminary encasement prevents any potential leakage paths from forming, ensuring device reliability even as the airgap is subsequently created.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between the gate and source/drain contacts, minimizing RC delay and power dissipation while preventing gate current leakage by creating air spacers within dielectric layers.
Implementation Method 1
depositing a dielectric material in the enlarged sacrificial region to form an airgap between a remaining portion of the contact spacer and the gate structure
Data Source
AI summary
A semiconductor device includes a gate having a gate spacer formed on a semiconductor substrate and a source or drain (S/D) formed on the substrate a distance away from the gate. A S/D contact including a contact spacer is formed on an upper surface of the S/D. A dielectric layer is interposed between the gate spacer and the contact spacer; and an airgap is in the dielectric layer.