Air-gap Spacer for Vertical FET Gate Length Control
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Solution Overview
Problem
Vertical transistors face challenges in controlling gate length precision and parasitic capacitance due to conventional fabrication processes, which affect device performance.
Innovation Solution
The use of an airgap spacer formed over a vertical transistor's channel region, combined with a two-material fin structure, to reduce parasitic capacitance and enable precise control of gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a top spacer is used to separate the top source/drain region from the gate, then device structure is defined, but parasitic capacitance increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material by using air (dielectric constant ≈ 1) instead of conventional dielectric materials (dielectric constant > 3). This parameter change reduces parasitic capacitance between the gate and source/drain regions while maintaining the structural definition function of the spacer.
Solution Approach 2:
The patent employs a composite structure where air gaps are integrated within the spacer formation. The spacer consists of conventional dielectric material in some regions and air gaps in other regions, creating a composite structure that provides both structural definition and low parasitic capacitance properties.
2Ease of manufacture
If conventional fabrication processes are used, then manufacturing is simplified, but gate length variation increases
Solution Approach 1:
The patent implements a self-aligned fabrication process where the air gap spacer automatically positions itself relative to the gate structure during formation. The spacer material is deposited conformally and then anisotropically etched, causing the air gaps to form precisely at the gate edges without requiring additional alignment steps. This self-service mechanism achieves high gate length precision while maintaining fabrication simplicity.
Solution Approach 2:
The patent performs preliminary formation of the air gap spacer structure before final gate patterning. By pre-establishing the spacer geometry and air gap positions, the subsequent gate formation process inherits this precise positioning, reducing gate length variation without adding complex alignment steps.
Data Source
AI summary
A transistor includes a channel fin. A gate stack is formed on sidewalls of the channel fin. A top spacer is formed over the gate stack. The top spacer includes dielectric material that fully encapsulates air gaps directly above the gate stack. A top source/drain region formed on the channel fin.