Airgap TSV Interconnects for Ultra-Low Capacitance
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Solution Overview
Problem
Current Through Silicon Via (TSV) interconnects in semiconductor devices have high capacitance, which is not sufficient for certain applications, particularly in high-speed and high-density interconnects, necessitating a reduction in capacitance to achieve ultra-low values below 50 fF.
Innovation Solution
The formation of airgaps in a trench-like structure surrounding the TSV interconnects, specifically using a trench-like ring structure with a conductive pillar made of materials like copper or nickel, and sealing the airgaps with insulating dielectric materials to reduce capacitance, allowing for ultra-low capacitance TSVs independent of silicon substrate thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a ring structure is filled with dielectric material surrounding a conductive TSV interconnect, then the structural integrity is improved, but the capacitance of the interconnect structure increases
Solution Approach 1:
The patent extracts the dielectric material from the region immediately surrounding the TSV interconnect and replaces it with air gaps. This removal of dielectric material directly reduces the capacitance while the conductive cage structure maintains the necessary structural integrity and mechanical support for the interconnect
Solution Approach 2:
The patent applies different material properties to different regions: air gaps are used in the immediate vicinity of the TSV interconnect to minimize capacitance, while dielectric material is retained in outer regions to provide structural support. This localized differentiation optimizes both capacitance reduction and structural integrity
2Speed
If the density of chip input/output connection pads is increased to meet high-speed requirements, then the bandwidth is improved, but the capacitance of interconnects increases
Solution Approach 1:
The patent converts the harmful effect of closely spaced I/O pads (which increases capacitance) into a benefit by introducing air gaps. The same high-density pad layout that causes capacitance issues is now managed by the air gap structure, which isolates the TSV interconnect from capacitive coupling to surrounding structures, allowing high-density interconnects to achieve ultra-low capacitance
3Ease of manufacture
If conventional TSV structures are used without airgaps, then the manufacturing process is simpler, but the capacitance is too high for certain applications
Solution Approach 1:
The patent incorporates air gap formation into the existing TSV manufacturing process flow at an early stage. The air gaps are created during the same processing steps used to form the TSV structure itself, using the existing mask and etch processes, thereby adding minimal complexity to the manufacturing while achieving the required ultra-low capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of 3D-TSV interconnects with ultra-low capacitance, suitable for high-speed digital, high-frequency RF applications, and memory stacking, by effectively reducing capacitance to values well below 10 fF, enhancing performance in dense interconnect environments.
Implementation Method 1
the density of chip input/output connection pads (I/O's) continues to increase. This leads to an increasing bandwidth of interconnects between integrated circuits (IC's) and/or other system elements. For short interconnects, electrical signal lines maintain the highest capacity and speed.
Implementation Method 2
sealing the airgaps with insulating dielectric materials to reduce capacitance
Data Source
Figure 1a~2
Figure 3a~3b
Figure 4a~4b
AI summary
Ultra-low capacitance interconnect structures, preferably Through Silicon Via interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate (1) having a first main surface (S1), producing at least one hollow trench-like structure (R1) therein from the first main surface (S1), said trench-like structure surrounding an inner pillar structure (22) of substrate material, depositing a dielectric liner (24) which pinches off said hollow trench-like structure (R1) at the first main surface (S1) such that an airgap is created in the center of hollow trench-like structure (R1) and further creating a TSV hole (23) and filling it at least partly with conductive material.