Airgap Integration Via Self Alignment and Shorting Improvement
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Solution Overview
Problem
Integrated circuit structures face challenges with capacitive coupling between closely spaced wiring lines, which slows data transmission rates and increases energy consumption, particularly due to misaligned conductive vias in air gaps that can lead to shorting and reliability issues in interconnects.
Innovation Solution
The implementation of airgaps between metal lines using a sacrificial material and selective etching techniques to create voids, combined with dual damascene patterning and hardmask materials to ensure precise alignment and prevent shorting, while using porosity in hardmask materials for mass transport and etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If air gaps are formed between adjacent metal lines to reduce capacitive coupling, then data transmission rates improve and energy consumption decreases, but misaligned vias can cause shorting and reduce interconnect reliability
Solution Approach 1:
A mask layer is introduced as an intermediary between the via and the air gap. The mask layer prevents direct contact between misaligned vias and the air gap, eliminating the shorting risk while preserving the capacitive coupling reduction benefits of the air gap structure.
Solution Approach 2:
The mask layer is formed beforehand to prevent the harmful effect of via-to-air-gap shorting before it can occur. By preemptively blocking the potential shorting path, the design allows air gaps to be used without compromising reliability.
2Reliability
If masks are used to prevent formation of air gaps where vias are present, then shorting is prevented, but the implementation of air gaps is limited particularly in lower interconnect levels with higher via density
Solution Approach 1:
The mask layer is selectively positioned only in regions where vias are present, rather than uniformly across the entire structure. This localized approach prevents shorting at via locations while allowing air gaps to be formed in other regions, thereby maintaining air gap benefits in high-via-density areas without compromising reliability.
3Ease of manufacture
If conventional dielectric materials are used between wiring lines, then manufacturing is simpler, but capacitive coupling increases which slows data transmission and increases energy consumption
Solution Approach 1:
The dielectric constant parameter of the material between wiring lines is changed from conventional high-k dielectric materials to air (k≈1). This parameter change reduces capacitive coupling, thereby improving data transmission rates and reducing energy consumption while maintaining manufacturing feasibility through the mask-based air gap formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive coupling, enhances data transmission rates, and improves interconnect reliability by maintaining airgaps and preventing shorting between metal lines, thereby improving the performance of integrated circuits.
Implementation Method 1
using porosity in hardmask materials for mass transport and etch selectivity
Implementation Method 2
forming airgaps between metal lines using a sacrificial material and selective etching techniques to create voids
Data Source
AI summary
A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.