AIS FEC Coding Without Bit-Stuffing for Reliable Transmission
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Solution Overview
Problem
The Automatic Identification System (AIS) for maritime navigation faces challenges with transmission errors due to noise and interference, and the integration of forward error correction (FEC) coding is hindered by bit-stuffing and cyclic redundancy check (CRC) complexities, requiring a method to enhance error correction while maintaining AIS standard compliance.
Innovation Solution
A method involving bit erasing to compensate for run length limitations in FEC-coded binary sequences, allowing for FEC coding without additional bit insertion, and using trellis termination sequences to maintain AIS compliance, along with iterative demodulation and decoding to improve error correction and acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction (FEC) coding is integrated into AIS, then transmission reliability is improved, but device complexity increases due to bit-stuffing and CRC complexities
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing valid FEC-coded sequences that already satisfy AIS run-length limitations in a lookup table during system initialization. This allows the transmitter to directly retrieve pre-validated sequences without performing real-time bit-stuffing operations, thereby improving transmission reliability through FEC while avoiding the complexity of dynamic bit-stuffing and CRC validation mechanisms
Solution Approach 2:
The patent implements beforehand cushioning by incorporating run-length limitation constraints into the FEC code design itself. The lookup table stores only those FEC-coded sequences that inherently satisfy the maximum run-length requirements, providing a buffer that prevents violation of AIS specifications without requiring additional real-time checking or correction mechanisms
2Adaptability or versatility
If bit-stuffing is used to enforce run length limitations, then AIS standard compliance is maintained, but transmission efficiency deteriorates due to additional bit insertion
Solution Approach 1:
The patent eliminates the need for runtime bit-stuffing operations by pre-generating and storing in the lookup table only those FEC-coded bit sequences that already satisfy the AIS run-length limitations. When transmission is required, the system directly retrieves a compliant sequence from the table without performing any additional bit insertion operations, thereby maintaining AIS standard compliance while preserving transmission efficiency
Solution Approach 2:
The patent extracts and removes the bit-stuffing operation from the transmission pipeline by incorporating the run-length constraint satisfaction directly into the codebook generation process. The lookup table contains only valid sequences, effectively taking out the need for dynamic bit insertion and leaving only the efficient lookup and transmission operations
3Measurement precision
If additional training sequences are added for acquisition, then acquisition performance is improved, but message length increases
Solution Approach 1:
The patent applies universality by designing the lookup table to simultaneously serve multiple functions: it provides FEC error correction, ensures run-length compliance, and incorporates synchronization information. The pre-validated sequences in the table are constructed to maintain inherent synchronization properties, allowing the system to achieve reliable acquisition without adding separate training sequences, thereby improving acquisition performance while avoiding message length increase
Data Source
AI summary
The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.