AIS Message Coding With FEC and Bit-Stuffing Compensation
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Solution Overview
Problem
The Automatic Identification System (AIS) for maritime navigation faces issues with signal misdetection due to transmission errors and interference, which existing technologies struggle to address effectively, particularly due to the complexity of integrating forward error correction (FEC) coding with bit-stuffing and cyclic redundancy check (CRC) processes while maintaining compliance with AIS standards.
Innovation Solution
The method involves coding the AIS message using FEC codes, performing bit erasure to ensure run-length limitation without additional bits, and adding trellis termination sequences to facilitate error correction and improved acquisition, while ensuring the transmitter waveform remains compliant with AIS standards by compensating for bit-stuffing effects and using additional training sequences for better signal acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction (FEC) coding is integrated with bit-stuffing and CRC processes, then error correction capability is improved, but system complexity increases
Solution Approach 1:
The patent segments the AIS message structure into distinct components: FEC coded data portion, uncoded header portion, and CRC field. This segmentation allows different error protection strategies to be applied to different parts of the message, improving overall reliability while managing complexity through modular design
Solution Approach 2:
The patent applies preliminary bit-stuffing compensation before FEC encoding by erasing specific bits in the data portion. This preliminary action prepares the data to accommodate potential bit-stuffing operations while maintaining the ability to perform accurate FEC decoding and CRC verification
2Manufacturing precision
If bit-stuffing is applied to limit run lengths, then signal compliance with AIS standards is improved, but additional bits are inserted increasing message length
Solution Approach 1:
The patent performs preliminary bit erasure in the data portion before FEC encoding, strategically removing bits that would trigger bit-stuffing operations. This preliminary action reduces the likelihood of additional bits being inserted during transmission while ensuring compliance with AIS run-length limitations
Solution Approach 2:
The patent modifies the bit pattern in the data portion by erasing specific bits to change the run-length parameters. This parameter change reduces consecutive identical bits, ensuring compliance with AIS bit-stuffing requirements while minimizing the need for additional stuffing bits
3Device complexity
If non-coherent detection is used for simple receiver structures, then receiver complexity is reduced, but signal-to-noise ratio requirements increase
Solution Approach 1:
The patent applies FEC coding and strategic bit erasure before transmission to cushion against the limitations of non-coherent detection. This beforehand protection compensates for the higher SNR requirements by providing error correction capability that mitigates the impact of simple receiver structures
Solution Approach 2:
The patent employs CRC verification and FEC decoding feedback mechanisms that allow the receiver to detect and correct errors even with non-coherent detection. This feedback loop compensates for the lack of phase information by using redundancy to recover the original message
Data Source
AI summary
The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.