III-V FET Gate Structures with ALD Dielectric Fill
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Solution Overview
Problem
The existing Tee-gate structure in III-V semiconductor FETs suffers from increased parasitic capacitances and processing difficulties due to air gaps, complex resist profile formation, and crevice formation under the gate, which impede effective passivation and device performance.
Innovation Solution
A semiconductor structure with a recess and a dielectric film having an aperture, where the electric contact is formed through atomic layer deposition (ALD) of TiN or Ni, decoupling gate patterning and etch processes, eliminating air gaps and crevices, and allowing conformal coverage without the need for complex resist profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Tee-gate structure is used in double recessed device, then gate control is achieved, but parasitic gate to drain and gate to source capacitances increase significantly
Solution Approach 1:
The patent extracts and removes the air gaps from beneath the gate electrode by filling the recess with dielectric material. This eliminates the harmful capacitance coupling between the gate and substrate that occurs through air, thereby reducing parasitic gate-to-source and gate-to-drain capacitances while maintaining gate control functionality.
Solution Approach 2:
The patent introduces a dielectric material as an intermediary substance between the gate electrode and the substrate. This dielectric layer acts as a mediator that reduces electrical coupling and parasitic capacitance while still allowing the gate to control the channel, effectively decoupling the harmful electrical interaction.
2Manufacturing precision
If direct E-beam write method is used to form Tee-gate, then gate pattern is formed, but throughput reduces to less than 4 wafers per hour
Solution Approach 1:
The patent segments the gate formation process into separate steps: first forming the gate electrode pattern using conventional lithography, then separately filling the recess with dielectric material and forming the passivation layer. This segmentation allows each step to be optimized independently and enables higher throughput by avoiding the need for complex direct E-beam writing.
Solution Approach 2:
The patent performs preliminary patterning of the gate electrode using conventional lithography before forming the complete Tee-gate structure. This preliminary action establishes the gate pattern using high-throughput methods, and subsequent steps simply add the dielectric fill and passivation layers without requiring complex resist writing.
3Reliability
If evaporated Ti/Pt/Au or Ni/Pt/Au is used for Tee-gate, then Schottky contact is formed, but severe crevices are formed underneath which impede SiN passivation layer coverage
Solution Approach 1:
The patent inverts the conventional sequence: instead of forming the metal gate electrode first and then attempting to cover crevices with passivation, it first forms the gate electrode, fills the recess with dielectric material, and then forms the passivation layer over the flat top surface. This inversion eliminates the crevice coverage problem by preventing crevice formation in the first place.
Solution Approach 2:
The patent extracts and removes the crevice-forming mechanism by changing the deposition sequence. By filling the recess with dielectric material before forming the passivation layer, the harmful crevices that would impede passivation coverage are eliminated, allowing complete and uniform passivation layer formation.
4Manufacturing precision
If dielectric is used for transfer of stem pattern in hybrid gate approach, then pattern transfer is achieved, but etching of dielectric and semiconductor becomes extremely critical with excessive undercut or damage
Solution Approach 1:
The patent uses the gate electrode itself as a self-aligned mask for forming the recess, eliminating the need for separate dielectric pattern transfer steps. The gate electrode pattern is copied directly into the recess structure through self-aligned etching, avoiding the complexity of controlling dielectric etching and preventing undercut issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitances and processing complexities, enabling more efficient and stable gate formation with improved conformal coverage and reduced etching damage, enhancing the performance and stability of III-V semiconductor FETs.
Implementation Method 1
Atomic Layer Deposition (ALD) technique is used in the deposition of thin films of metals and dielectric in which there is precise, atomic level, control of the film thickness and conformality
Data Source
AI summary
A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.