Al Interface Dipoles in High-k Gate Stacks for pMOSFET Work Function Tuning
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Solution Overview
Problem
The scaling of metal oxide semiconductor field effect transistors (MOSFETs) to sub-50 nm dimensions leads to increased leakage current and polysilicon depletion effects, making it difficult to tune the work function of p-type metal gate devices effectively, as traditional gate stacks with silicon oxide and polysilicon are inadequate.
Innovation Solution
A semiconductor device and manufacturing method involving a gate stack with a high k gate dielectric layer and metal gate electrode, where aluminum (Al) is introduced at the upper and bottom interfaces of the gate dielectric and electrode, forming Al-O electric dipoles through thermal annealing, which adjusts the energy levels and tunes the work function of pMOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional gate stacks with silicon oxide and polysilicon are used, then manufacturing is simpler, but leakage current increases exponentially and polysilicon depletion effect becomes severe at sub-50 nm dimensions
Solution Approach 1:
The patent employs composite gate stack structures combining high-k dielectric materials (such as HfO2, Al2O3, TiO2) with metal gate electrodes (such as TiN, TaN, WN). This composite approach replaces the traditional silicon oxide/polysilicon stack, providing both low leakage current and elimination of polysilicon depletion effects while maintaining manufacturability through established deposition techniques.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate stack by introducing high-k dielectric materials with higher permittivity values and metal gates with adjustable work functions. This parameter transformation enables reduced equivalent oxide thickness with lower leakage and eliminates the depletion effect inherent in polysilicon gates.
2Reliability
If single element metal materials with high work function (e.g., platinum, gold) are used for pMOSFET, then work function requirement is met, but etching becomes extremely difficult and cost increases significantly
Solution Approach 1:
The patent uses composite metal gate structures such as TiN/HfN, TaN/WN, or MoN/HfN combinations. These composite metal gates provide work functions suitable for pMOSFET (around 5.2 eV) while maintaining excellent etchability and compatibility with standard CMOS fabrication processes, avoiding the use of expensive and difficult-to-etch noble metals like platinum or gold.
Solution Approach 2:
The patent applies different metal materials with complementary properties in specific locations within the gate electrode stack. For example, a bottom metal layer provides mechanical support and adhesion, while a top metal layer provides the required work function, optimizing both electrical performance and manufacturability locally within the gate structure.
3Reliability
If high k gate dielectric layer with Al interface layers is used, then work function tuning is achieved, but device structure becomes more complex
Solution Approach 1:
The patent introduces aluminum-containing interface layers (such as Al2O3, AlN, or Al-doped dielectric layers) specifically at the critical interfaces between the high-k dielectric and metal gate, or between the high-k dielectric and semiconductor substrate. This localized modification provides effective work function tuning and interface quality improvement without requiring complex modifications throughout the entire device structure.
Solution Approach 2:
The patent forms aluminum-containing interface layers during the gate stack fabrication process before final metal gate deposition. This preliminary action prepares the interface with appropriate work function characteristics and reduces interface states, enabling subsequent processing steps to proceed with standard materials and processes, thereby limiting complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current, eliminates polysilicon depletion effects, and allows for precise tuning of the work function of p-type metal gates, enhancing device performance by shifting the flat-band voltage and increasing the gate work function.
Implementation Method 1
the element Al combines with O to form Al—O electric dipoles
Implementation Method 2
forming Al-O electric dipoles through thermal annealing, which adjusts the energy levels and tunes the work function
Implementation Method 3
forming Al-O electric dipoles through thermal annealing
Data Source
AI summary
The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.