Alarm System CPU Load Reduction via DMA Data Transfer
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Solution Overview
Problem
Existing alarm systems face increased CPU load due to simultaneous execution of multiple functions, leading to inefficiencies and potential power consumption issues.
Innovation Solution
An information processing device with an internal storage device, serial communication unit, D/A converter, and CPU that uses direct memory access to transfer dummy and reproduction data, reducing CPU load by allowing the serial communication unit and D/A converter to communicate independently of the CPU, thereby minimizing CPU involvement in data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processor executes programs to realize multiple functions (event detector, transmission processor, reception processor, alarm processor) simultaneously, then the alarm system can perform comprehensive monitoring and communication, but the load on the processor increases
Solution Approach 1:
The patent segments the alarm system into distinct functional modules: event detector, transmission processor, reception processor, and alarm processor. Each module is implemented as a separate program that can be independently executed or activated based on system needs, allowing comprehensive functionality while managing processor load through selective execution rather than simultaneous operation of all functions
Solution Approach 2:
The processor is designed to perform multiple roles by executing different programs for event detection, data transmission, data reception, and alarm generation. This multi-functional approach allows a single processor to handle diverse tasks, reducing the need for separate dedicated hardware for each function while maintaining system versatility
2Reliability
If the CPU directly manages data transfer between storage devices and communication units, then data control is precise, but the CPU load and power consumption increase
Solution Approach 1:
The patent introduces a data bus as an intermediary component that facilitates data transfer between the processor, external storage device, and communication units. This bus-based architecture allows automated data movement without requiring continuous CPU intervention for each byte transfer, reducing power consumption while maintaining reliable data control through protocol-managed communication
Data Source
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AI summary
An object of the present invention would be to propose an information processing device capable of suppressing an increase in a load on a CPU and an alarm system including the same. An internal storage device (2) holds dummy data (D1). A serial communication unit (3) obtains, from an external storage device (11) holding reproduction information including multiple pieces of reproduction data (D3), the multiple pieces of reproduction data (D3), by obtaining the dummy data (D1) from the internal storage device (2) and sending the dummy data (D2) to the external storage device (11). A D/A converter (4) obtains the multiple pieces of reproduction data (D4) from the serial communication unit (3) and converts a digital signal into an analog signal (A1) for each of the multiple pieces of reproduction data (D4). A CPU (5) controls the serial communication unit (3). The serial communication unit (3) obtains the dummy data (D1) from the internal storage device (2) by DMA thereto. The D/A converter (4) obtains the multiple pieces of reproduction data (D4) from the serial communication unit (3) by DMA thereto.