ALD Dielectric Chip Passivation for Humidity-Rugged Packaging

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Solution Overview

Problem

Power semiconductor devices face failure due to corrosion and degradation in humid environments and high temperature reverse bias tests, with existing solutions either being sensitive to charges or expensive and prone to cracking.

Innovation Solution

A chip arrangement with a second dielectric layer formed by atomic layer deposition (ALD) over a first dielectric layer, providing a barrier against humidity and mobile ions, and acting as an adhesion promoter for encapsulants, which includes materials like Al2O3, SiO2, and HfO2 to create a dense and stable moisture barrier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thick hard passivation layer is applied to improve humidity ruggedness, then corrosion protection is enhanced, but the layer becomes expensive and prone to cracking

Engineering Contradiction:

Improvehumidity ruggednessVSAvoidpassivation layer complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The passivation structure is divided into multiple layers: a first dielectric layer (e.g., silicon oxide) providing base protection, and a second dielectric layer (e.g., silicon nitride) deposited by ALD providing enhanced humidity barrier. This segmentation allows each layer to perform specific functions, achieving superior humidity ruggedness without the drawbacks of a single thick layer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses composite dielectric structures combining different materials (e.g., silicon oxide and silicon nitride) with complementary properties. The ALD-deposited second dielectric layer provides dense, pinhole-free protection that complements the first dielectric layer, creating a composite structure that resists humidity and mobile ions more effectively than single-material layers.

Inventive Principle:

Principle #40Composite materials

2Reliability

If voltage limiting devices are used at metal edges to improve humidity ruggedness, then corrosion protection is enhanced, but the termination area becomes sensitive to charges and HTRB stability is compromised

Engineering Contradiction:

Improvehumidity ruggednessVSAvoidHTRB stability

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The ALD-deposited second dielectric layer acts as an intermediary barrier between the metal contact pads and the humid environment. This layer provides charge compensation and prevents charge accumulation at the metal edges, thereby maintaining HTRB stability while still providing excellent humidity protection. The ALD layer serves as a mediator that decouples the conflicting requirements of humidity ruggedness and HTRB stability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If existing passivation approaches are used, then some level of protection is achieved, but cost increases and manufacturing complexity increases

Engineering Contradiction:

Improvecorrosion protectionVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The invention replaces complex mechanical/passivation structures with an ALD-deposited dielectric layer that provides superior protection through atomic-level deposition. The ALD process creates a conformal, pinhole-free barrier that is more effective than traditional thick passivation layers, reducing the need for additional protective structures and simplifying the overall manufacturing process.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents corrosion and degradation of metal and isolation layers, enhances humidity ruggedness, and prevents HTRB failures, while being cost-effective and suitable for molded packages.

Implementation Method 1

a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad

Methodology Applied

Scientific EffectAtomic layer deposition: Physical Vapour Deposition

Data Source

PatentUS20230274996A1Chip arrangement, chip package, method of forming a chip arrangement, and method of forming a chip package

Publication Date: 2023.08.31 INFINEON TECHNOLOGIES AG

AI summary

A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.