ALD Die-to-Die Interconnects for CMP Pad Spacing Variation
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Solution Overview
Problem
Conventional semiconductor device packaging processes, such as hybrid bonding, face challenges with inconsistent spacing between conductive pads due to chemical-mechanical planarization (CMP) processes, leading to under-expanded or over-expanded interconnects, which can result in voids or reduced mechanical strength, affecting the reliability and robustness of the semiconductor device.
Innovation Solution
The use of atomic layer deposition (ALD) to form interconnects between conductive pads in stacked semiconductor devices, allowing for precise control of the conductive material deposition between pads, even with misalignment, and the use of spacers to maintain spacing, reducing the risk of under- or over-expanded interconnects and enhancing the reliability of the semiconductor device assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical planarization (CMP) process is used to prepare conductive pads, then planarity of the pad surface is improved, but spacing consistency between pads deteriorates due to dishing effects
Solution Approach 1:
The patent changes the deposition parameters by using atomic layer deposition (ALD) with controlled deposition rates and multiple cycles to compensate for pad dishing. The ALD process deposits material layer-by-layer with precise control over thickness and uniformity, counteracting the non-uniform pad surfaces created by CMP and ensuring consistent interconnect spacing despite variations in pad topography.
2Reliability
If hybrid bonding is used to form interconnects, then electrical coupling between dies is achieved, but reliability deteriorates due to under-expanded or over-expanded interconnects from inconsistent pad spacing
Solution Approach 1:
The patent replaces the thermal-mechanical expansion process of hybrid bonding with a controlled deposition process. Instead of relying on thermal expansion to push pads together, the invention uses atomic layer deposition to precisely build up conductive material in the gaps between pads, eliminating the need for thermal expansion and its associated variability.
Solution Approach 2:
The invention changes the fundamental process parameters from thermal-mechanical expansion to controlled material deposition. By using ALD with precisely controlled deposition rates, temperatures, and cycle numbers, the process achieves consistent interconnect formation without the variability inherent in thermal expansion-based hybrid bonding.
3Object-affected harmful factors
If conventional packaging processes are used, then die protection is achieved, but mechanical strength deteriorates due to voids and poor interconnect formation
Solution Approach 1:
The patent replaces the mechanical pressure-based interconnect formation with a deposition-based approach. Atomic layer deposition fills the gaps between pads with conformal layers of conductive material, creating solid, void-free interconnects that maintain mechanical strength while providing electrical coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ALD process enables the formation of reliable and robust interconnects with precise control, reducing the risk of interconnect failures and improving the mechanical strength and reliability of the semiconductor device assembly by allowing for a larger margin of error in pad alignment and dishing, while also adapting to different conductive materials.
Implementation Method 1
a conductive material is disposed between the first conductive pad and the second conductive pad (e.g., through ALD) to implement an interconnect
Data Source
AI summary
A semiconductor device assembly is provided. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a first layer of dielectric material and a first conductive pad disposed in a first opening of the first layer of dielectric material. The second semiconductor die has a second layer of dielectric material facing the first layer of dielectric material and a second conductive pad disposed in a second opening of the second layer of dielectric material and corresponding to the first conductive pad. A spacer extends between the first layer of dielectric material and the second layer of dielectric material. A conductive material is disposed between the first conductive pad and the second conductive pad (e.g., through atomic layer deposition (ALD)) to implement an interconnect electrically coupling the first semiconductor die and the second semiconductor die.