Integrated ALD and Etch for FinFET Gate Profile Control
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in maintaining precise control over gate etching in FinFET devices due to issues with etch byproduct re-deposition and lateral critical dimension loss, particularly at 3D corners, which affects device performance and integrity.
Innovation Solution
An integrated method of performing in-situ atomic layer deposition (ALD) and etch processes in a plasma chamber, where a conformal passivation layer is deposited using ALD on exposed surfaces after partial gate etching, followed by selective etching to the top surface of an insulating material layer, minimizing etch byproduct re-deposition and maintaining vertical profiles with minimal lateral CD loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional separate etch and deposition processes are used, then processing time and costs increase, but manufacturing precision and control over gate etching improve
Solution Approach 1:
The patent combines separate etch and deposition processes into a single integrated plasma chamber, allowing sequential etching and ALD deposition without chamber transfer. This merging eliminates processing time losses while maintaining manufacturing precision through in-situ process control and immediate transition between steps.
Solution Approach 2:
The integrated process enables continuous operation within the plasma chamber, eliminating vacuum breaks and chamber transfer interruptions. The useful action continues seamlessly from etching to deposition, improving productivity while maintaining process control through uninterrupted in-situ monitoring.
2Productivity
If multiple chamber transfers are performed, then processing time increases, but material exposure to unwanted substances decreases
Solution Approach 1:
By merging etch and deposition operations into a single plasma chamber, the patent eliminates multiple chamber transfers that would expose materials to contaminants during transfer. The integrated system maintains a controlled environment throughout the entire process sequence.
Solution Approach 2:
The plasma chamber provides a controlled, inert processing environment that protects materials from unwanted substances during the entire etch-deposition sequence. By performing all operations within this controlled atmosphere without external transfers, the patent minimizes contamination risks.
3Reliability
If gate layer is etched to define gate structures, then device performance improves, but lateral critical dimension loss and residual material at 3D corners occur
Solution Approach 1:
The patent applies a thin conformal passivation layer on the gate layer before etching to protect sidewalls and prevent lateral CD loss. This preliminary protective action ensures precise critical dimension control during the gate etch process while maintaining device performance.
Solution Approach 2:
The conformal passivation layer acts as an intermediary protective layer during gate etching, preventing direct contact between the etchant and the gate structure sidewalls. This mediator layer eliminates residual material at 3D corners and maintains vertical profiles while allowing the etch to proceed to define the gate structures.
4Manufacturing precision
If conformal passivation layer is deposited by ALD, then etch byproduct re-deposition is minimized, but processing complexity increases
Solution Approach 1:
The patent integrates ALD deposition capability into the plasma chamber, combining etch and deposition functions in one system. This merging eliminates the need for separate deposition equipment while achieving conformal passivation layer deposition that minimizes etch byproduct re-deposition.
Solution Approach 2:
The integrated plasma chamber performs both etching and ALD deposition functions, making the system self-sufficient for the complete etch-deposition sequence. This self-service capability reduces the need for additional separate equipment and simplifies the overall process architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing time and costs, minimizes material exposure to unwanted substances, and ensures precise control over gate and fin structures, enhancing the integrity and performance of FinFET devices by avoiding residual material at 3D corners and maintaining vertical profiles.
Implementation Method 1
etching, in a plasma chamber, a gate layer of a FinFET semiconductor device
Implementation Method 2
etching, in a plasma chamber
Implementation Method 3
introducing a precursor into the plasma chamber to adsorb on the gate layer and the one or more top surfaces of the one or more corresponding semiconductor fins
Implementation Method 4
converting the precursor with a plasma to form an adsorption-limited amount of the first passivation layer
Data Source
AI summary
Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.