Atomic Layer Deposition and Etch for Reducing Line Edge Roughness
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in reducing line edge roughness (LER) and line width roughness (LWR) during the fabrication of advanced integrated circuits, leading to adverse impacts on device performance and critical dimension control, particularly as feature sizes shrink.
Innovation Solution
The method involves integrating atomic layer deposition (ALD) and etch processes in a plasma chamber to deposit conformal layers on patterned mask layers, reducing roughness by forming patterned features with improved LER and LWR values, and applying passivation layers to minimize sidewall roughness in high aspect ratio features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If current patterning methods are used to fabricate small critical dimension features, then device features can be patterned at small sizes, but surface roughness and line edge roughness increase adversely impacting device performance
Solution Approach 1:
A conformal layer is deposited on the patterned mask layer before the etch process to smooth the surface. This preliminary action reduces surface roughness and line edge roughness before patterning the material layer, ensuring that the etched features inherit the smoothness from the conformal layer rather than the rough mask layer.
Solution Approach 2:
The conformal layer acts as an intermediary between the rough patterned mask layer and the material layer being etched. It transfers a smooth surface profile to the underlying material, decoupling the roughness of the mask from the smoothness required in the final patterned features.
2Manufacturing precision
If treatment techniques are applied to reduce roughness from patterning, then surface roughness decreases, but critical dimensions of patterned features are adversely affected
Solution Approach 1:
The conformal layer is deposited with uniform thickness across different regions (isolated features vs. dense features), providing localized smoothing without introducing global critical dimension bias. This ensures that both isolated and dense features maintain consistent critical dimensions after etching.
Solution Approach 2:
The ALD process parameters are controlled to deposit a conformal layer with thickness between 0.5 nm and 5 nm, which is sufficient to smooth surface roughness but thin enough to not significantly alter critical dimensions. This parameter optimization resolves the contradiction between roughness reduction and CD preservation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces LER and LWR to values equal to or less than 2.0 nm, maintaining critical dimension consistency across different feature densities and materials, thereby enhancing semiconductor device performance and reducing the risk of defects like short-circuiting and increased resistivity.
Implementation Method 1
introducing a precursor into the plasma chamber to adsorb on the patterned mask layer
Implementation Method 2
converting the precursor with plasma to form an adsorption-limited amount of the first conformal layer
Implementation Method 3
etching, in the plasma chamber, the first material layer to form a plurality of first patterned features
Data Source
AI summary
Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.