ALD Etch-Stop Layer Structure for High Breakdown Voltage Vias
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Solution Overview
Problem
The challenges of reduced dielectric layer thickness in semiconductor fabrication lead to lower breakdown voltages, pinholes causing electrical shorts, and increased RC delay due to decreased capacitance in integrated circuits, particularly in advanced technology nodes.
Innovation Solution
Employing atomic layer deposition (ALD) processes to form etch-stop layers (ESLs) using aluminum oxide, which provide high breakdown voltage, reduced pinholes, and lower dielectric constant, minimizing oxidation and ion bombardment effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dielectric layer thickness is reduced to increase functional density, then production efficiency is improved, but breakdown voltage decreases and reliability deteriorates
Solution Approach 1:
The patent changes the material composition parameters of the dielectric layer by incorporating aluminum oxide (Al2O3) and silicon oxycarbide (SiOxCy) with specific ratios. This material parameter change enables the dielectric layer to maintain high breakdown voltage (exceeding 8.5 MV/m) even at reduced thickness, thus resolving the contradiction between increased productivity through scaling and maintained reliability
Solution Approach 2:
The patent employs a composite dielectric material system combining aluminum oxide and silicon oxycarbide. This composite structure leverages the high breakdown voltage特性 of aluminum oxide and the low dielectric constant特性 of silicon oxycarbide, achieving both high reliability and reduced RC delay simultaneously while maintaining thin layer thickness for high productivity
2Productivity
If dielectric layer thickness is reduced to increase functional density, then production efficiency is improved, but pinholes cause electrical shorts
Solution Approach 1:
The patent optimizes deposition parameters including temperature control (250-350°C for ALD), precursor flow rates, and deposition time to achieve pinhole-free thin films. The controlled deposition process ensures complete coverage and eliminates pinholes even in ultra-thin dielectric layers, maintaining high productivity while preventing electrical shorts
Solution Approach 2:
The patent replaces conventional physical vapor deposition methods with atomic layer deposition (ALD) and chemical vapor deposition (CVD) processes. These chemical deposition methods provide superior film conformality and defect control, eliminating pinholes through controlled chemical reactions that ensure complete and uniform coverage at the molecular level
3Productivity
If dielectric layer thickness is reduced to increase functional density, then production efficiency is improved, but RC delay increases
Solution Approach 1:
The patent changes the dielectric material composition to achieve a low dielectric constant (k-value) of approximately 2.65 by incorporating silicon oxycarbide. This parameter change reduces the capacitance in the interconnect structure, thereby reducing RC delay and allowing thinner dielectric layers to be used without compromising signal integrity, enabling continued scaling for high productivity
4Ease of manufacture
If conventional deposition methods are used to form dielectric layers, then manufacturing process is simpler, but metal oxidation increases
Solution Approach 1:
The patent replaces physical vapor deposition (PVD) with atomic layer deposition (ALD) and chemical vapor deposition (CVD) methods. These chemical deposition techniques occur in controlled atmospheres that minimize oxygen exposure to underlying metal layers, significantly reducing metal oxidation while maintaining manufacturing feasibility through standardized semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ALD-deposited ESLs enhance device reliability by increasing breakdown voltage, reducing electrical shorts, and lowering RC constant, while maintaining film quality and minimizing metal oxidation.
Implementation Method 1
employing atomic layer deposition (ALD) processes to form etch-stop layers (ESLs)
Data Source
AI summary
The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.