Low Temperature ALD Gate Oxide for FinFET Spacing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate stacks in FINFET technology face issues with uncontrolled fin to fin spacing, breakdown voltage deterioration, and bridge defects due to the thinning of gate dielectric as the gate length decreases, necessitating a conformal low temperature oxide solution.
Innovation Solution
A method involving the formation of conformal low temperature gate oxide layers on high voltage input/output and core logic devices, using a sequence of silicon oxy-nitride and hafnium oxide layers, with specific deposition and etching processes to achieve controlled fin spacing and breakdown voltage, including plasma-enhanced atomic layer deposition and remote plasma treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate dielectric is thinned to maintain performance with decreased gate length, then the device can be scaled to smaller dimensions, but uncontrolled fin to fin spacing and bridge defects occur
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first gate oxide layer for conformal coverage, a silicon oxy-nitride layer for spacing control, and a second gate oxide layer for final gate dielectric function. This segmentation allows each layer to perform its specific function independently, enabling precise fin-to-fin spacing control while maintaining scaled dimensions.
Solution Approach 2:
The silicon oxy-nitride layer acts as an intermediary between the first and second gate oxide layers. It provides a controlled etch stop and defines the fin-to-fin spacing during processing, preventing bridge defects while allowing the final gate dielectric to be optimally thin for scaled performance.
2Length of moving object
If the gate dielectric is thinned to maintain performance with decreased gate length, then device scaling is enabled, but breakdown voltage deteriorates
Solution Approach 1:
The gate stack uses a composite structure combining silicon dioxide (first gate oxide layer) and silicon oxy-nitride layers. The silicon oxy-nitride layer has superior breakdown characteristics compared to pure silicon dioxide, allowing the overall gate dielectric to be thinner while maintaining or improving breakdown voltage reliability.
Solution Approach 2:
Different regions of the gate stack have different material compositions optimized for different functions: the first gate oxide layer provides conformal coverage, the silicon oxy-nitride layer provides high breakdown strength and spacing control, and the second gate oxide layer provides the final gate dielectric function. This local optimization allows thinning for scaling while maintaining reliability.
3Length of moving object
If conventional gate stacks are used with decreased gate length, then device scaling is possible, but uncontrolled fin to fin spacing occurs
Solution Approach 1:
The first gate oxide layer is formed preliminarily before the final gate structure is complete. This preliminary layer provides a conformal base that ensures uniform fin-to-fin spacing from the outset, preventing spacing control issues that would arise if the gate structure were formed first and then thinned.
Solution Approach 2:
The invention changes the physical and chemical parameters of the gate stack by introducing silicon oxy-nitride layers with specific nitrogen concentrations (3-12% nitrogen). This parameter change allows for precise control of etch rates and deposition characteristics, enabling uniform fin spacing control during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables controlled fin to fin spacing, well-regulated breakdown voltage, and reduced bridge defects, allowing for the scaling of FINFETs while maintaining performance, and is applicable to the 7 nanometer technology node and beyond.
Implementation Method 1
forming ALD silicon dioxide (SiO2) by plasma-enhanced atomic layer deposition (PEALD) or thermal ALD at a temperature of 385° C. to 425° C.
Implementation Method 2
performing a remote plasma treatment using oxygen (O2) or ozone (O3) gas to generate radical O2 for ALD SiO2 growth
Implementation Method 3
forming a first silicon oxy-nitride layer by: plasma nitridation at a room temperature and up to 450° C. with 9% to 12% of nitrogen (N)
Implementation Method 4
removing the sacrificial oxide layer by dilute hydrofluoric acid (dHF) etching
Implementation Method 5
thinning the first gate oxide layer to a thickness of 22 Å to 35 Å by wet etching, wherein the wet etching includes a 100:1 dHF solution
Data Source
AI summary
Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.