ALD and PVD TaN Barrier Layer Conformity
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Solution Overview
Problem
Conventional methods for forming barrier layers in integrated circuit back-end-of-the-line interconnect structures often damage underlying dielectric materials, produce non-conformal or discontinuous layers, and result in high resistivity and susceptibility to impurities.
Innovation Solution
The method involves using a combination of atomic layer deposition (ALD) and physical vapor deposition (PVD) processes to form a robust barrier layer by depositing tantalum nitride (TaN) layers, with the ALD process creating a conformal first layer and the PVD process densifying the upper portion to enhance density and reduce resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form barrier layers, then the formation process is simple and fast, but the barrier layers are non-conformal, discontinuous, or too thin/thick in different regions
Solution Approach 1:
The barrier layer formation is segmented into multiple deposition steps using different techniques (ALD and PVD). The ALD process deposits a thin conformal layer first, then the PVD process adds additional material. This segmentation allows each process to contribute its strengths: ALD provides conformality while PVD adds material efficiently.
Solution Approach 2:
The patent changes deposition parameters by switching between two different deposition techniques with distinct characteristics. ALD operates at lower temperatures with atomic-level precision for conformal coverage, while PVD provides higher deposition rates. By adjusting the sequence and parameters of these processes, optimal barrier layer properties are achieved.
2Productivity
If conventional deposition methods are used to form barrier layers, then the process is faster, but the underlying dielectric material is damaged
Solution Approach 1:
The patent controls deposition parameters by using ALD at lower temperatures to avoid dielectric damage, then follows with PVD which can operate at higher temperatures without affecting the already-formed conformal barrier layer. This parameter control protects the dielectric while maintaining productivity.
3Manufacturing precision
If thin barrier layers are formed, then the resistivity is lower, but the layers are too thin or discontinuous particularly along vertical walls
Solution Approach 1:
The barrier layer is formed in segments: first a thin conformal ALD layer provides continuous coverage and reliability, then an additional PVD layer is added to achieve the target thickness while maintaining the continuity established by the ALD layer.
Solution Approach 2:
The barrier structure becomes a composite of two different deposition layers with complementary properties. The ALD layer provides conformal coverage and continuity, while the PVD layer contributes to overall thickness and density, creating a robust composite barrier structure.
4Reliability
If conventional single-process deposition is used, then the process is simpler, but the barrier layers have high resistivity and are susceptible to impurity damage
Solution Approach 1:
The deposition process is segmented into ALD followed by PVD. The ALD process creates a dense, impurity-resistant base layer with excellent conformality, while the subsequent PVD process adds material that maintains this impurity resistance while achieving the required thickness. This segmentation provides superior impurity protection compared to single-process deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a continuous, high-density barrier layer that protects the dielectric material and is less susceptible to impurity damage, improving the integrity and performance of the interconnect structure.
Implementation Method 1
A first tantalum nitride (TaN) layer is deposited into the via-hole overlying the metal line using an atomic layer deposition (ALD) process
Implementation Method 2
A second TaN layer is deposited into the via-hole overlying the first TaN layer using a physical vapor deposition (PVD) process to form a barrier layer
Data Source
AI summary
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.