ALD Spacer Formation for High-k Gate Uniformity
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Solution Overview
Problem
Conventional methods for depositing spacers around high-k metal gate structures in integrated circuits result in non-uniform spacer thicknesses across isolated and dense device areas, leading to electrical variations due to temperature-related diffusion and leakage issues.
Innovation Solution
The use of atomic layer deposition (ALD) processes with specific precursor cycles and dual-layer spacer formation, where the first spacer layer is deposited at a lower temperature and the second at a higher temperature, providing improved wet etch resistance and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PECVD processes are used to deposit spacer layers at low temperatures, then diffusion of halo or extension implants or of layers containing oxygen is prevented from affecting electrical properties of the high-k gate insulator, but non-uniform spacer thicknesses are obtained across isolated and dense device areas
Solution Approach 1:
The patent changes the deposition temperature parameter from conventional low temperatures to elevated temperatures (600-900°C) during ALD processing. This parameter change enables uniform spacer formation across isolated and dense device areas while maintaining protection of high-k gate insulator electrical properties through the use of oxide spacer material and controlled deposition conditions
Solution Approach 2:
The patent substitutes PECVD deposition with Atomic Layer Deposition (ALD) methodology. This replacement enables precise control of spacer thickness and uniformity through sequential precursor exposure and self-limiting surface reactions, achieving conformal coverage and consistent thickness across varying device densities
2Manufacturing precision
If spacer deposition is performed at elevated temperatures, then uniform spacer thickness is achieved across isolated and dense device areas, but diffusion of halo or extension implants or of layers containing oxygen may affect electrical properties of the high-k gate insulator
Solution Approach 1:
The patent optimizes the deposition temperature parameter within a specific range (600-900°C) to achieve uniform spacer formation while controlling diffusion effects. This temperature window enables sufficient adatom mobility for uniform coverage without excessive diffusion that would compromise high-k gate insulator electrical properties
Solution Approach 2:
The patent replaces conventional PECVD with ALD methodology, which provides superior control over deposition kinetics and film properties. The self-limiting nature of ALD surface reactions enables uniform spacer formation at controlled rates, reducing unwanted diffusion while maintaining thickness uniformity across isolated and dense device areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in highly uniform spacers with reduced thermal budget, minimizing electrical variations and enhancing device reliability by maintaining sufficient resistance to etchants while reducing thermal exposure.
Implementation Method 1
An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternately flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
Implementation Method 2
A first atomic layer deposition (ALD) process is performed at no more than about 200° C. to deposit a first spacer layer around the gate structure. A second ALD process is performed to deposit a second spacer layer around the first spacer layer.
Data Source
AI summary
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.