ALD Via Sidewall Protection for High Aspect Ratio Etching
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Solution Overview
Problem
As semiconductor substrate geometries shrink, the increased aspect ratios of vias and the use of skip vias complicate the etching process, leading to 'bowing' profiles in dielectric layers, which obstruct proper conductor formation and reduce via yield.
Innovation Solution
The implementation of an atomic layer deposition (ALD) process to form protective layers on via sidewalls during etching, specifically for low k and ultra-low k dielectric layers, mitigates bowing by separating the ALD process from etching steps and using multiple ALD layers to protect dielectric layers during barrier etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for high aspect ratio vias, then via etching can be performed, but bowing profiles occur in dielectric layers reducing via yield
Solution Approach 1:
A sacrificial spacer layer is deposited on the via sidewalls to act as an intermediary protective barrier during etching. This spacer layer prevents direct plasma exposure of the dielectric sidewalls, eliminating bowing while allowing complete via etching. The spacer is subsequently removed, leaving a straight via profile without compromising yield.
Solution Approach 2:
The sacrificial spacer layer is deposited before the via etching process begins. This preliminary action prepares the sidewalls with protective coverage that will be removed after etching, ensuring straight profiles are maintained throughout the etching process without affecting final via dimensions.
2Productivity
If aspect ratios of vias are increased due to geometry shrinkage, then higher density integration is achieved, but etching difficulty and profile control become more challenging
Solution Approach 1:
The sacrificial spacer serves as a mediator that enables etching of high aspect ratio vias by providing continuous sidewall protection throughout the etch process. This allows the etching of deeper, narrower vias required for high density integration without the bowing that would otherwise make such vias impossible to form with straight profiles.
Solution Approach 2:
The introduction of the sacrificial spacer changes the etching process parameters by adding a protective layer that modifies plasma interaction with the dielectric. This parameter change enables control over sidewall profiles during high aspect ratio etching, making the process feasible for dense interconnect structures.
3Adaptability or versatility
If skip vias are used to connect through multiple dielectric layers, then conductor layer connectivity is improved, but via aspect ratio and profile control difficulty increase
Solution Approach 1:
The sacrificial spacer layer acts as a mediator that enables skip via formation through multiple dielectric layers by providing continuous protection during the extended etching process. This allows skip vias to maintain straight profiles despite the increased etch depth and multiple layer penetrations required for conductor connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures straight sidewall profiles for high aspect ratio vias, reduces bowing, and integrates easily into standard process flows with controlled ALD layer thickness and material composition, enhancing via formation quality and yield.
Implementation Method 1
performing an atomic layer deposition (ALD) process to deposit a protective layer on via sidewalls
Data Source
AI summary
A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.