Atomic Layer Etch Hard Mask Smoothing for EUV Lithography
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Solution Overview
Problem
EUV lithography in semiconductor fabrication faces challenges such as shot noise and secondary electron exposure, leading to random variations in photon interactions, resulting in blurring of feature edges, line edge roughness, and inadequate control over critical dimensions, particularly at sub-7 nanometer technology nodes.
Innovation Solution
Implementing a cyclic atomic layer etch process that includes a surface modification step to convert a portion of the hard mask layer and a selective removal step, allowing for precise control over feature dimensions and reducing surface roughness, using a combination of plasma processes to form and remove a modified layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If EUV lithography is used to pattern features at sub-7 nanometer nodes, then higher resolution patterns can be achieved, but shot noise and secondary electron exposure cause random variations in photon interactions, resulting in blurring of feature edges and line edge roughness
Solution Approach 1:
The patent segments the etching process into multiple atomic layer etch (ALE) cycles, where each cycle consists of a surface modification step followed by a removal step. This segmentation allows precise control of material removal at the atomic level, addressing the precision loss caused by EUV lithography shot noise and secondary electron effects.
Solution Approach 2:
The surface modification step in each ALE cycle performs preliminary action by converting the top layer of the hard mask material into a different phase or composition before removal. This preliminary modification enables selective removal in the subsequent step, achieving atomic-level precision in defining feature edges despite EUV lithography limitations.
2Device complexity
If conventional lithography and etching processes are used, then the fabrication process is simpler, but precise dimension control at the nanometer range cannot be achieved
Solution Approach 1:
The patent replaces conventional plasma etching (a bulk removal process) with atomic layer etching, which uses sequential chemical reactions at the atomic level. This substitution of the etching mechanism enables precise dimension control at the nanometer and atomic scale, though it increases process complexity through multiple cyclic steps.
3Productivity
If feature sizes are shrunk to double the component packing density, then higher packing density is achieved, but various fabrication challenges are intensified
Solution Approach 1:
The patent changes the fundamental parameter of material removal from bulk plasma etching to atomic-layer sequential modification and removal. This parameter change enables precise control of feature dimensions even as feature sizes are shrunk to achieve higher packing density, addressing the intensified fabrication challenges at smaller nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of feature dimensions and reduces surface roughness, improving the ability to control critical dimensions at the nanometer level, thereby addressing the limitations of EUV lithography in semiconductor fabrication.
Implementation Method 1
In a plasma process chamber, executing a self-limiting atomic layer etch process to modify the hard mask layer
Implementation Method 2
forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer
Data Source
AI summary
In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.