Atomic Layer Etching for Re-entrant Semiconductor Profiles
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Solution Overview
Problem
The semiconductor industry faces challenges in metal-filling operations due to increasing complexity and aspect ratios of semiconductor structures, leading to issues with profile control and reliability in forming semiconductor structures with re-entrant profiles, which affects the manufacturing of devices like FinFETs.
Innovation Solution
The use of atomic layer etching (ALE) with gradual adjustments in reactive gas flow rates, pressure, and temperature to form semiconductor structures with re-entrant profiles, enhancing selectivity and preventing bowing profiles, thereby improving metal-filling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching methods are used to form openings in semiconductor structures, then the manufacturing process is simple, but the profile control deteriorates and bowing profiles occur due to high aspect ratios
Solution Approach 1:
The etching process is divided into multiple sequential atomic layer etching (ALE) cycles, where each cycle consists of a reaction step followed by a termination step. This segmentation allows precise control over the etching depth and profile by repeating the cycle multiple times, preventing bowing profiles while maintaining manufacturing feasibility.
Solution Approach 2:
The ALE process employs periodic alternation between reaction gas exposure and termination gas exposure. The reaction gas (e.g., CF4, SF6) etches the semiconductor material, while the termination gas (e.g., O2, N2) stops the etching by passivating the surface. This periodic action enables precise profile control by adjusting the number and duration of cycles.
2Device complexity
If metal filling is performed in structures with high aspect ratios, then device complexity increases, but filling reliability deteriorates due to profile loading variations
Solution Approach 1:
The ALE process performs preliminary profile preparation by creating a re-entrant profile with wider opening than bottom. This preliminary action of shaping the opening profile before metal filling ensures that subsequent metal deposition and filling operations proceed reliably without profile loading variations, even in high aspect ratio structures.
Solution Approach 2:
The ALE process changes physical parameters including gas flow rates, pressure, and temperature to optimize etching conditions. By adjusting these parameters, the process achieves consistent etching rates and profile control, which directly improves metal filling reliability in complex high aspect ratio structures.
3Reliability
If selectivity to hard mask layers is increased, then gate loss prevention improves, but process complexity increases
Solution Approach 1:
The ALE process uses intermediary gas layers and chemistry to achieve high selectivity. The reaction gas selectively reacts with the semiconductor material while the termination gas selectively passivates the surface, creating a controlled etching process that spares the hard mask layer. This intermediary approach prevents gate loss without requiring complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of semiconductor structures with high selectivity to hard mask layers, preventing gate loss and improving the reliability of semiconductor devices by facilitating consistent metal filling and reducing profile loading variations.
Implementation Method 1
atomic layer etching (ALE) with gradual adjustments in reactive gas flow rates, pressure, and temperature
Implementation Method 2
performing an ionized noble gas bombardment on the portion of the SoC layer
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.