AlGaN/GaN CMOS Transistor Layers Without Post-Growth Annealing
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Solution Overview
Problem
GaN transistors face challenges in achieving high power and high frequency operations due to difficulties in p-doping and post-growth annealing, which can degrade transistor performance and require complex processing.
Innovation Solution
The use of semiconductor layers with varying aluminum content in AlGaN or GaN transistors, where every second layer has a lower aluminum content than its neighbors, reduces the need for post-growth annealing and enhances p-doping, leading to improved hole concentration and mobility, enabling more efficient and flexible transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-growth annealing is used to activate p-doping in GaN, then hole concentration is improved, but transistor performance degrades and manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by designing the semiconductor layer structure with alternating aluminum content during the growth phase itself, rather than requiring post-growth annealing. The alternating low-aluminum-content layers are configured to automatically enhance p-doping effectiveness during growth, eliminating the need for subsequent annealing processes while achieving the desired hole concentration and avoiding performance degradation
Solution Approach 2:
The patent changes the aluminum content parameter in the semiconductor layers by creating alternating layers with different aluminum concentrations. This parameter variation during growth modifies the material properties to enhance p-doping effectiveness intrinsically, replacing the need for external thermal processing and simplifying the manufacturing process while maintaining reliable hole concentration
2Reliability
If post-growth annealing is performed to remove passivation, then doping activation is improved, but material diffusion occurs and transistor performance degrades
Solution Approach 1:
The patent performs the doping activation action during the epitaxial growth process itself through the alternating layer structure, rather than relying on post-growth annealing. The low-aluminum-content layers are designed to facilitate dopant activation intrinsically during growth, preventing the need for subsequent thermal processes that would cause material diffusion and composition changes
Solution Approach 2:
By varying the aluminum content parameter in alternating layers during growth, the patent creates conditions that promote dopant activation without requiring high-temperature annealing. This parameter modification during growth achieves doping activation while maintaining material profile stability, as the layers are formed with controlled compositions that prevent diffusion
3Ease of manufacture
If conventional GaN transistor design is used, then manufacturing is simpler, but power efficiency and operating frequency are limited
Solution Approach 1:
The patent modifies the aluminum content parameter in the semiconductor layers to create alternating high and low aluminum-content layers. This parameter variation enhances hole concentration and mobility, enabling improved power efficiency and higher operating frequencies while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The patent uses composite semiconductor layer structures combining AlGaN layers with different aluminum compositions. This composite approach creates materials with enhanced electrical properties for improved power efficiency and frequency operation, while the layered structure can be integrated into conventional manufacturing workflows
4Speed
If higher hole concentration is achieved through conventional means, then switching speed is improved, but manufacturing complexity and annealing requirements increase
Solution Approach 1:
The patent achieves higher hole concentration by changing the aluminum content parameter in alternating semiconductor layers during growth. This structural parameter modification inherently enhances hole concentration and mobility, enabling faster switching speeds without requiring complex post-growth processing or annealing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in transistors with higher hole concentration and mobility, facilitating faster switching and higher operating frequencies, and allows for the production of power-efficient CMOS devices without the need for post-growth annealing, enabling smaller transistor sizes and improved manufacturing flexibility.
Implementation Method 1
The plurality of semiconductor layers may enhance the p-doping through a variation in the valence-band edge, as described by Kozodoy et al. [Appl. Phys. Lett. 75, 2444 (1999)]. The variation in the valence-band edge is herein caused by the variation in Al content in the plurality of semiconductor layers.
Implementation Method 2
Ballistic transport may be achieved by superlattices of AlGaN/GaN heterostructures at specific alloy compositions of AlGaN.
Data Source
AI summary
A transistor (1) comprising a source (10), a body (12) and a drain (14), the transistor (1) further comprising a plurality of semiconductor layers (20), wherein layers of the plurality of semiconductor layers (20) are made of AlGaN or GaN, and wherein the plurality of semiconductor layers (20) is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof, wherein the transistor (1) is either a N-channel metal-oxide-semiconductor, NMOS, transistor (1′), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the body (12) of the NMOS transistor (1′); or a P-channel metal-oxide-semiconductor, PMOS, transistor (1″), wherein part of the plurality of semiconductor layers (20) is p-doped and forms part of the source (10) or the drain (14) of the PMOS transistor (1″).