Hardware Design Verification for Algebraic Expression Decomposition
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Solution Overview
Problem
Existing methods for verifying hardware designs that evaluate algebraic expressions face scalability issues, particularly when dealing with expressions involving many input variables or large bit widths, leading to convergence problems during formal verification.
Innovation Solution
The approach involves decomposing the algebraic expression into a lossless combination of sub-algebraic expressions, constraining the hardware design to evaluate each sub-expression, and then formally verifying these sub-expressions and their combinations to ensure the main expression is correctly evaluated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on the entire algebraic expression, then verification completeness is improved, but verification time and computational resources increase exponentially
Solution Approach 1:
The patent divides the algebraic expression into multiple sub-expressions that can be verified independently. The verification process is segmented into verifying each sub-expression separately and then verifying the combination of sub-expressions, rather than verifying the entire expression as a single unit. This segmentation reduces the exponential complexity of verifying the complete expression while maintaining verification completeness through systematic decomposition and recombination of verification results.
2Measurement precision
If the hardware design is verified against a high-level model, then verification accuracy is improved, but the complexity of setting up and managing test signals increases
Solution Approach 1:
The patent segments both the hardware design and the high-level model into corresponding sub-expressions. By verifying each sub-expression pair independently, the complexity of managing test signals for the entire system is broken down into manageable subsets. This approach maintains verification accuracy through detailed sub-expression level comparison while reducing the overall complexity of test signal management through modular verification units.
3Ease of manufacture
If simulation-based verification is used, then ease of implementation is improved, but verification coverage becomes insufficient for complex expressions
Solution Approach 1:
The patent combines simulation-based verification advantages with formal verification completeness by segmenting the verification process. Simulation is used for individual sub-expressions where exhaustive testing is feasible, while formal verification methods are applied to verify the structural correctness of sub-expression combinations. This segmented approach achieves both ease of implementation through simulation and comprehensive coverage through formal methods, overcoming the limitations of using either approach alone.
Data Source
AI summary
A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.