Algorithm Integrating System for BIST Circuit Optimization
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Solution Overview
Problem
The existing memory test processes for integrated circuits are inefficient due to high complexity and cost, particularly in systems with multiple types of memory, where individual input of test orders increases testing time and complexity, and built-in self-test (BIST) circuits often require extensive area on the chip while providing inadequate fault coverage.
Innovation Solution
An algorithm integrating system comprising a receiving module, analyzing module, and processing module that identifies and integrates non-duplicate basic elements from test algorithms to optimize the built-in self-test (BIST) circuit, reducing chip area, test time, and cost while enhancing fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all test algorithms are built in the BIST circuit, then fault coverage is improved, but chip area cost is highly increased
Solution Approach 1:
The patent segments test algorithms into basic elements (read operation, write operation, compare operation, pass/fail judgment) that can be independently selected and combined. This allows the BIST circuit to include only necessary test functions rather than all possible algorithms, reducing chip area while maintaining adequate fault coverage through modular composition of test capabilities.
Solution Approach 2:
The patent creates a universal BIST circuit framework that can perform multiple test functions through combination of basic elements. The circuit is designed to be multi-functional, capable of implementing various test algorithms by differentially combining read, write, compare, and judgment operations, thereby achieving high fault coverage without requiring separate dedicated circuits for each test algorithm.
2Adaptability or versatility
If individual test orders are input from ATE, then test flexibility is improved, but control and communication complexity increases
Solution Approach 1:
The patent implements self-service by enabling the BIST circuit to autonomously generate and execute test sequences internally without requiring external ATE control for each test operation. The built-in circuit automatically manages test flow, reducing communication overhead and control complexity while maintaining test flexibility through programmable algorithm selection.
3Device complexity
If built-in self-test circuit is added to memory, then communication complexity with ATE is reduced, but chip area is increased
Solution Approach 1:
The patent segments the BIST circuit into essential functional modules (pattern generator, comparator, counter, control logic) that perform core self-test functions. By implementing only these segmented essential functions rather than complete test algorithm implementations, the circuit achieves communication independence while minimizing chip area occupation.
4Area of stationary object
If redundant test algorithms are removed, then chip area is reduced, but test time may increase
Solution Approach 1:
The patent merges multiple test operations into unified basic elements that can be executed efficiently. By combining read, write, compare, and judgment operations into integrated basic blocks, the circuit achieves compact implementation that reduces both area and test time, as these merged operations can be performed in sequence without requiring separate dedicated circuits for each function.
Data Source
AI summary
The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.