Algorithm Integrity Verification via Dual Execution and Memory Segmentation
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Solution Overview
Problem
Existing methods for protecting the integrity of algorithm execution against fault injection attacks are either costly due to the need for dual processing devices or inefficient as they require multiple executions on the same device, lacking a cost-effective solution for transparent integrity verification.
Innovation Solution
A method involving a processing unit that performs a calculation twice, with the results stored in different zones of volatile memory, and a memory management circuit that intercepts and transforms write requests into read requests for comparison, allowing for fault detection without additional hardware or separate execution paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two processing devices are used to detect fault injection attacks, then the reliability of execution integrity is improved, but the material cost increases
Solution Approach 1:
The patent merges the functions of two separate processing devices into a single processing unit by implementing redundant execution logic within one device. The processing unit executes the same algorithm multiple times with different initial states or configurations, allowing fault detection without requiring duplicate hardware devices, thus reducing material cost while maintaining execution integrity verification
Solution Approach 2:
The patent creates virtual copies of the execution process by running the algorithm multiple times within the same processing unit. These copies use different internal states or configurations but share the same physical hardware, enabling comparison of results to detect faults without needing additional physical devices
2Quantity of substance
If the same processing device is used to execute the algorithm twice, then the material cost is reduced, but the execution time increases
Solution Approach 1:
The patent implements periodic execution of the algorithm where the processing unit runs the same computational task multiple times in succession. By structuring these executions to overlap or pipeline certain operations, and by using different initial configurations that may converge to the same result, the system verifies integrity through repeated execution while managing the time overhead through efficient scheduling
Solution Approach 2:
The patent performs preliminary setup of different execution configurations before running the algorithm multiple times. By pre-configuring different initial states, data arrangements, or computational paths that are known to produce consistent results under normal operation, the system reduces the overhead of setting up each execution from scratch, thereby reducing total execution time while maintaining verification capability
3Difficulty of detecting and measuring
If results are stored in different zones of volatile memory, then the detection capability is improved, but the device complexity increases
Solution Approach 1:
The patent segments the volatile memory into distinct zones or regions for storing results from different execution instances. This segmentation allows the system to easily track and compare results from multiple executions by their storage location, improving fault detection capability. The memory management circuit automatically handles the mapping of execution instances to specific memory zones, managing the complexity through systematic organization rather than ad-hoc management
4Measurement precision
If write requests are transformed into read requests for comparison, then the fault detection accuracy is improved, but the processing complexity increases
Solution Approach 1:
The patent introduces a memory management circuit as an intermediary between the processing unit and the volatile memory. This intermediary intercepts write requests from the processing unit, transforms them into read requests to retrieve previously stored results, and performs comparison operations. By centralizing this transformation logic in a dedicated circuit, the patent improves fault detection accuracy through systematic comparison while managing processing complexity through specialized hardware rather than general-purpose software routines
Data Source
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AI summary
The invention relates to a method of executing an algorithm, comprising the following steps: performing (41) a first execution (EXE1) of the algorithm by a processing unit (11); sending at least one first result for writing to a memory to a memory management circuit; storing (43) said first result in a first area (122) of volatile memory; performing (44) a second execution (EXE2) of the algorithm by said processing unit; sending at least one second result for writing to the memory of said circuit; and applying (46, 47, 48), by said circuit, a different processing compared to the first execution.