Algorithm Pattern Generator for Memory Testing
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Solution Overview
Problem
Conventional memory testers require expensive and large equipment for high-speed, high-accuracy testing of DRAMs, leading to high manufacturing costs and a need for miniaturization and cost optimization.
Innovation Solution
An algorithm pattern generator with address scrambling and data scrambling capabilities, integrated into a memory tester configuration, which includes an instruction memory, sequence control unit, interface unit, PLL, command generating unit, address generating unit, data generating unit, and data comparing unit, to optimize the test pattern generation and reduce equipment size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory testers are used for high-speed, high-accuracy DRAM testing, then test accuracy is improved, but equipment size and manufacturing cost increase
Solution Approach 1:
The patent combines address scrambling and data scrambling functions into a single integrated ALPG device, eliminating the need for separate scrambling equipment. The ALPG generates both address and data patterns simultaneously, reducing the number of components and equipment size while maintaining high-accuracy testing capability.
Solution Approach 2:
The ALPG device performs multiple functions including address pattern generation, data pattern generation, address scrambling, and data scrambling within a single unit. This multi-functional design replaces what would traditionally require multiple separate devices, thereby reducing equipment size and cost while preserving test accuracy.
2Measurement precision
If conventional memory testers are used for high-speed, high-accuracy DRAM testing, then test accuracy is improved, but manufacturing cost increases
Solution Approach 1:
By integrating address scrambling and data scrambling into a single ALPG device, the patent reduces the total component count and simplifies the manufacturing process. This consolidation leads to lower manufacturing costs while maintaining the high-accuracy testing required for DRAM validation.
Solution Approach 2:
The ALPG generates test patterns through algorithmic computation rather than requiring complex hardware configurations. The device uses programmable logic to create address and data patterns, which simplifies manufacturing compared to dedicated hardware approaches, thereby reducing production costs while preserving test accuracy.
3Productivity
If test speed is increased for higher productivity, then productivity is improved, but test accuracy may deteriorate
Solution Approach 1:
The ALPG pre-generates and pre-scrambles both address and data patterns before they are applied to the memory device under test. This preliminary pattern generation allows the testing process to proceed at high speeds without compromising accuracy, as the complex scrambling operations are performed in advance rather than in real-time during the actual test.
Solution Approach 2:
The ALPG continuously generates and updates test patterns at high frequency, maintaining continuous useful action during the testing process. This continuous pattern generation enables high-speed testing while preserving accuracy through consistent and uninterrupted pattern application to the memory device.
Data Source
AI summary
Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.