1.5-Bit Algorithmic ADC Using One Comparator for Lower Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 1.5-bit algorithmic analog-to-digital converters (ADCs) require significant power and silicon area due to the use of two comparators and differential difference comparators, which are complex and prone to malfunction when common mode voltages differ, leading to increased complexity and power consumption.
Innovation Solution
A 1.5-bit algorithmic ADC architecture that uses a single differential comparator and implements a series of conversion cycles with scaling and sampling sub-cycles, generating two-bit code pairs that are mapped to digital values through shift-and-add operations, reducing complexity and power consumption while maintaining resilience to voltage offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 1.5-bit algorithmic ADCs use two comparators to define three voltage regions, then voltage offset resilience is improved, but power consumption and silicon area increase significantly
Solution Approach 1:
The patent combines the functions of two separate comparators into a single differential comparator. The differential comparator directly compares the differential input signal against a reference voltage, merging the comparison functions that were previously distributed across two independent comparators. This consolidation maintains the ability to define multiple voltage regions while reducing power consumption and component count.
Solution Approach 2:
The single differential comparator is designed to perform multiple functions: it compares differential signals, defines voltage regions, and provides offset resilience. By making the comparator multi-functional, the patent eliminates the need for separate comparators while maintaining all necessary comparison capabilities for 1.5-bit algorithmic conversion.
2Reliability
If conventional 1.5-bit algorithmic ADCs use two differential difference comparators, then voltage offset resilience is improved, but device complexity increases
Solution Approach 1:
The patent merges two complex differential difference comparators into a single differential comparator structure. This single comparator handles the differential comparison task that previously required two separate comparators, thereby reducing device complexity while maintaining the same level of voltage offset resilience through its differential architecture.
3Reliability
If conventional 1.5-bit algorithmic ADCs use two comparators, then voltage offset resilience is improved, but silicon area increases
Solution Approach 1:
The patent consolidates the silicon area requirements of two separate comparators into a single differential comparator. By merging the comparison functions into one integrated circuit block, the patent reduces the total silicon area occupied by comparator circuitry while preserving the voltage offset resilience that comes from using 1.5-bit algorithmic conversion.
4Reliability
If conventional 1.5-bit algorithmic ADCs use two differential difference comparators, then voltage offset resilience is improved, but implementation difficulty increases due to common mode voltage mismatches
Solution Approach 1:
Instead of using two separate comparators that each compare against reference voltages, the patent inverts the approach by using a single differential comparator that directly compares the differential input signal. This inversion of the comparison architecture eliminates the common mode voltage mismatch problem that arises when reference voltages have different common mode levels, while still achieving voltage offset resilience.
Data Source
AI summary
A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value.