Double Bandwidth Algorithmic Memory Array via XOR Parity Cascading
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Solution Overview
Problem
Conventional memory architectures, such as single-port and double-pumped memories, face limitations in bandwidth and complexity, particularly in achieving simultaneous read and write operations, which hinders high-speed data transfer in applications like data buffering and video processing.
Innovation Solution
A multi-banked memory architecture that incorporates a redundant array of independent disks (RAID) bank and a write buffer, utilizing XOR gates to cascade data and refresh parity bits, enabling one write or two reads per cycle, thereby doubling bandwidth capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-port memory is adopted to increase memory performance and enable simultaneous read/write operations, then bandwidth and productivity are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The memory array is divided into multiple banks (first memory bank, second memory bank, third memory bank) that can operate independently. Each bank can perform read or write operations simultaneously without interfering with others, enabling parallel data access and increasing overall bandwidth while maintaining manageable complexity through modular organization
Solution Approach 2:
A parity generation circuit is introduced as an intermediary component that calculates and stores parity bits for error detection. This mediator enables the system to achieve high bandwidth through parallel operations while maintaining data integrity, resolving the contradiction between performance and reliability without requiring complex error correction mechanisms in every data path
2Productivity
If double pumped memories are used to increase read speed, then productivity is improved, but the frequency doubling has practical hardware limitations
Solution Approach 1:
Instead of attempting to double the frequency of a single memory port, the system segments the memory into multiple banks that can operate in parallel. Each bank operates at the original frequency but the combined throughput is doubled, achieving the same productivity improvement without the hardware complexity of frequency doubling
Solution Approach 2:
The solution transitions from a single-dimensional frequency increase approach to a multi-dimensional parallel access approach. By adding temporal and spatial dimensions through multiple banks operating simultaneously, the system achieves higher bandwidth without increasing the operational frequency, thereby avoiding the practical hardware limitations of frequency doubling
Data Source
AI summary
The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.