Algorithmic TCAM Hash Relocation With Buffer-Based Address Updates
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Solution Overview
Problem
Ternary Content Addressable Memory (TCAM) systems require significant resources due to the need to represent ternary states (logic 0, logic 1, and X) using two-bit values in RAM, leading to inefficient use of resources.
Innovation Solution
The implementation of a content addressable memory circuit with shared memory address locations and buffer circuits, utilizing a hash table to assign hash values to memory address locations and relocate key values within the memory devices, allowing for efficient storage and retrieval of ternary data by using a combination of hash values to determine memory address locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-bit values are used to represent ternary states in RAM-based TCAM, then ternary data can be stored, but resource usage increases significantly
Solution Approach 1:
The patent segments the memory system into multiple memory devices with shared address locations, allowing parallel access and reducing the resource burden on individual devices. Each memory device handles a portion of the ternary data storage while sharing common address space, thereby reducing overall resource requirements per device.
Solution Approach 2:
The patent implements a universal address space that is shared across multiple memory devices, allowing the same address locations to be accessed simultaneously by different devices. This multi-functional approach enables efficient ternary data storage without requiring dedicated resources for each device, reducing total resource usage.
2Productivity
If content data is relocated within memory devices, then memory usage is optimized, but data access operations may be interrupted
Solution Approach 1:
The patent introduces buffer circuits as intermediary components between the memory devices and the external interface. These buffers temporarily hold data during relocation operations, allowing memory optimization through data movement while maintaining continuous data access for external operations without interruption.
Solution Approach 2:
The patent performs preliminary data copying to buffer circuits before initiating relocation operations within memory devices. This preliminary action ensures that data remains accessible during the relocation process, maintaining operational continuity while optimizing memory usage through subsequent relocation.
Data Source
AI summary
A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that corresponds to the first key value to the second memory address location of the memory device.