Aligned Gate-All-Around Structure for Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices, the reduction in channel length leads to short-channel effects, where the gate has reduced control over the channel, resulting in parasitic capacitance and inefficiencies due to the non-aligned second gate portion extending under the source and drain regions.
Innovation Solution
A gate-all-around structure is implemented with an aligned second gate portion formed within a cavity, using a dielectric layer to ensure self-alignment with the first gate portion, thereby preventing the second gate from overextending and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase circuit density, then the circuit density is improved, but the gate control over the channel deteriorates due to short-channel effects
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional gate-all-around structure that wraps around the channel in multiple dimensions. This vertical and lateral wrapping provides enhanced electrostatic control over the channel, effectively suppressing short-channel effects while maintaining reduced channel dimensions for high circuit density.
Solution Approach 2:
The gate structure is segmented into multiple portions including a first gate portion, a second gate portion, and a third gate portion that wrap around the channel at different locations. This segmentation allows each gate portion to independently control specific regions of the channel, improving overall gate control efficiency.
2Reliability
If the second gate portion extends under the source and drain regions to provide gate-all-around control, then the gate control is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies different structural characteristics to different regions of the gate structure. The second gate portion is positioned to provide necessary control over the channel region while being strategically limited from extending under the source and drain regions. This local differentiation maintains gate control effectiveness while minimizing parasitic capacitance generation in critical areas.
Solution Approach 2:
The patent extracts or removes the harmful extension of the second gate portion from under the source and drain regions. By carefully defining the boundaries of the second gate portion to stop before extending under these regions, the design eliminates the source of excessive parasitic capacitance while retaining the beneficial gate-all-around control over the channel.
Data Source
AI summary
A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion.