Aligned M1 Power Staples in Multi-Layer ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing design of multi-layer integrated circuits faces challenges in reducing the density and complexity of M1 power staples, which complicates the design process and results in staggered patterns and routing issues due to their placement within standard cells.
Innovation Solution
The proposed solution involves a standard cell architecture with M0 and M2 layers in horizontal orientation and M1 layers in vertical orientation, using a 3:2 M1/CPP gear ratio to position M1 power staples regularly without overlapping gate conductors, allowing for dense and aligned power staples that avoid conflicts with input or output contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If M1 power staples are added on each side of the standard cell boundary or in the design phase of standard cell placement, then power connection is achieved, but the density of M1 power staples is limited by the size of standard cells and the design process becomes complicated
Solution Approach 1:
The patent transitions from horizontal M1 power rails to vertical M1 power staples, changing the dimensional orientation of power connections. This vertical orientation allows power staples to connect M0 and M2 power rails through the standard cell layer without being constrained by horizontal routing limitations, thereby increasing power staple density and simplifying the design process by decoupling power grid design from standard cell IP design
Solution Approach 2:
The patent divides the power connection function into discrete M1 power staples positioned at specific locations (such as every other gate or at standard cell boundaries) rather than using continuous horizontal power rails. This segmentation allows for optimized power distribution while reducing design complexity and avoiding conflicts with signal routing
2Reliability
If M1 power staples are placed within standard cells, then power connection is achieved, but staggered M1 patterns result which create substantial patterning and routing challenges
Solution Approach 1:
The patent changes the positioning parameters of M1 power staples from arbitrary locations within standard cells to regularly spaced locations based on a recurring pattern (such as every other gate or at fixed intervals). This parameter change creates aligned M1 patterns that are consistent across the integrated circuit structure, thereby improving manufacturing precision and reducing patterning challenges
Data Source
AI summary
A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.