Aligned Semiconductor Vias via Simultaneous Etching
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Solution Overview
Problem
In semiconductor device manufacturing, misalignment of vias on metal wiring can lead to electrical short circuit failures due to reduced distance between adjacent metal wirings, causing connectivity issues.
Innovation Solution
The semiconductor device design includes a method where the via and metal wiring are simultaneously processed during etching, ensuring aligned side surfaces and maintaining a sufficient distance between them, thereby preventing short circuits. This involves forming a barrier metal and metal film on the insulating film, followed by etching to create the via and wiring, ensuring flat boundaries and adequate spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vias are formed on metal wiring using conventional processes, then via formation is achieved, but misalignment occurs causing reduced distance between adjacent metal wirings leading to electrical short circuit failure
Solution Approach 1:
The patent combines the formation of vias and metal wiring into a single simultaneous etching process. By using a unified etching step with a single mask pattern, the via holes and metal wiring grooves are created at the same time, ensuring their positions are inherently aligned and preventing the misalignment that would occur in sequential processes.
Solution Approach 2:
The patent forms the mask pattern that defines both via and wiring positions before the etching process begins. This preliminary mask formation establishes the precise spatial relationship between vias and metal wirings in advance, ensuring that when etching occurs, both features are created with correct alignment and spacing.
2Ease of manufacture
If via position is misaligned on metal wiring, then via formation is achieved, but the distance to adjacent metal wiring is shortened causing electrical short circuit
Solution Approach 1:
The patent merges via formation and metal wiring formation into one simultaneous etching operation. This unified process ensures that the distance between vias and adjacent metal wirings is precisely controlled by the single mask pattern, eliminating the distance control problems that arise when these features are formed in separate steps.
3Productivity
If conventional via formation process is used, then via is formed on metal wiring, but alignment error causes connectivity issues and short circuits
Solution Approach 1:
The patent combines via formation and metal wiring formation into a single etching process step. This unified approach maintains high productivity by completing both features in one operation while simultaneously improving electrical connectivity reliability through perfect alignment, as both features are created based on the same mask pattern without sequential alignment errors.
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first via provided on the semiconductor substrate; a metal wiring provided on the first via; and a second via provided on the metal wiring. One of the side surfaces facing each other in the first direction of the metal wiring and one of the side surfaces facing each other in the first direction of the second via are aligned in the first direction.