Fully Aligned Via Airgap Structure for TDDB-Safe Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in achieving reliable patterning at small dimensions due to poor overlay and the proximity of vias to unrelated metals, leading to issues like time-dependent dielectric breakdown and increased leakage.
Innovation Solution
A method is developed to form fully-aligned vias (FAVs) and airgaps within semiconductor devices at the same metallization level without using an additional airgap mask. This involves forming trenches, selectively removing inter-layer dielectric regions, and depositing a conformal cap and dielectric layer to create airgaps and align vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned via (SAV) processes are used, then via alignment is improved in one direction, but reliability deteriorates due to proximity to unrelated metal beneath causing time-dependent dielectric breakdown
Solution Approach 1:
The patent segments the dielectric space by introducing airgaps that physically separate the via from unrelated metal layers beneath it. This segmentation prevents the harmful electric field interaction that causes time-dependent dielectric breakdown, while maintaining via alignment through the self-aligned process.
Solution Approach 2:
The patent introduces an airgap as an intermediary layer between the via and the unrelated metal beneath it. This intermediary prevents direct electrical interaction and dielectric breakdown while allowing the via to remain aligned with the metal above through the self-aligned process.
2Reliability
If airgaps are formed using additional airgap mask, then airgap formation is achieved, but device complexity increases
Solution Approach 1:
The patent merges the via alignment process with the airgap formation process into a single self-aligned operation. By combining these two functions into one process step, the patent eliminates the need for separate airgap masks and reduces overall device complexity while maintaining both via alignment and airgap formation.
Solution Approach 2:
The patent makes the self-aligned via process multi-functional by enabling it to simultaneously perform both via alignment and airgap formation. This universal approach eliminates the need for dedicated airgap masks, reducing process steps and device complexity while achieving both objectives.
3Productivity
If dielectric space between copper lines and vias is reduced, then manufacturing density is improved, but reliability deteriorates due to proximity effects
Solution Approach 1:
The patent segments the dielectric space by introducing airgaps that physically separate conductive elements. This segmentation allows for reduced overall dielectric thickness (improving density) while preventing harmful interactions between nearby conductors that would compromise reliability.
Solution Approach 2:
The patent applies different local qualities to different regions: airgaps are introduced in specific locations where reliability concerns exist (near vias and unrelated metal), while maintaining reduced dielectric spacing in other regions to achieve high manufacturing density. This localized approach optimizes both density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitance in semiconductor devices, enhances thermal conductance and mechanical stability, and prevents reliability failures such as time-dependent dielectric breakdown, thereby improving the overall performance and reliability of semiconductor devices.
Implementation Method 1
depositing a conformal cap within the recesses, and depositing a dielectric layer such that the airgaps are formed in the airgap regions between the plurality of trenches
Data Source
AI summary
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.