Fully Aligned Via Integration Using Selective Graphene Deposition
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Solution Overview
Problem
The production of large-area graphene films for semiconductor applications is hindered by low surface coverage and high defect rates, with existing methods like thermal CVD causing physical damage to semiconductor materials due to elevated temperatures and requiring metal catalysts that lead to non-uniform layers and microstructural defects.
Innovation Solution
A method involving selective deposition of graphene on metal surfaces using remote hydrogen plasma CVD, followed by the deposition of an inhibitor layer and dielectric material, which inhibits deposition on barrier surfaces, allowing for high-quality graphene films to be grown at lower temperatures without damaging semiconductor substrates, and using graphene as an inhibitor to prevent dielectric material deposition on metal surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal CVD is used to deposit graphene, then graphene films can be produced, but physical damage occurs to semiconductor materials due to elevated temperatures
Solution Approach 1:
The patent changes the deposition temperature parameter from high (thermal CVD) to low (room temperature or near room temperature) by using a different mechanism (van der Waals epitaxy) to achieve graphene deposition without thermal damage to the semiconductor substrate
Solution Approach 2:
The patent replaces the thermal field (heat-based thermal CVD) with a field-based mechanism (van der Waals forces and electric field control) to deposit graphene, eliminating the need for high temperatures that cause substrate damage
2Productivity
If metal catalysts are used for graphene deposition, then graphene can be grown, but non-uniform layers and microstructural defects are created
Solution Approach 1:
The patent extracts and removes the metal catalyst component from the graphene deposition process, using van der Waals epitaxy on dielectric surfaces instead, which eliminates the source of non-uniformity and microstructural defects associated with metal catalysts
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary substrate that enables graphene deposition through van der Waals forces, providing a uniform surface that prevents the formation of defects and non-uniform layers while maintaining growth efficiency
3Quantity of substance
If existing methods are used to deposit graphene, then graphene films can be produced, but surface coverage is low and defect rates are high
Solution Approach 1:
The patent performs preliminary preparation of the dielectric surface (cleaning, activation, or functionalization) before graphene deposition to ensure optimal van der Waals interaction, which promotes complete surface coverage and reduces nucleation defects
Solution Approach 2:
The patent replaces thermal field-based deposition with field-based van der Waals epitaxy, which enables uniform graphene growth across the entire substrate surface without the high defect rates associated with thermal methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-quality, large-area graphene films with reduced defects and improved uniformity, suitable for semiconductor integration, by avoiding the use of metal catalysts and reducing temperature-related damage, while maintaining the electrical benefits of graphene.
Implementation Method 1
selectively depositing graphene on the exposed metal surface
Implementation Method 2
selectively depositing an inhibitor layer on the exposed barrier surface
Implementation Method 3
selectively depositing a dielectric material on the dielectric layer
Data Source
AI summary
Methods and apparatuses for an integration scheme for forming a fully aligned via using selective deposition of graphene on metal surfaces and selective deposition of an inhibitor layer on exposed barrier surfaces prior to depositing dielectric material are provided.