Fully Aligned Via Layout With Selective ILD Airgap Formation
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in achieving reliable patterning at small dimensions due to poor overlay and the proximity of vias to unrelated metals, leading to issues like time-dependent dielectric breakdown and increased leakage.
Innovation Solution
A method is developed to form fully-aligned vias (FAVs) and airgaps within semiconductor devices at the same metallization level without using an additional airgap mask. This involves forming trenches, selectively removing inter-layer dielectric (ILD) regions, and depositing a conformal cap and dielectric layer to create airgaps and align vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned via (SAV) processes are used, then via alignment is improved in one direction, but reliability deteriorates due to TDDB weak points forming near unrelated metals
Solution Approach 1:
The patent segments the dielectric layer into distinct regions: airgap regions where dielectric is completely removed to eliminate TDDB risks, and non-airgap regions where dielectric is retained for via formation. This segmentation allows simultaneous achievement of precise via alignment and reliability by spatially separating functions.
Solution Approach 2:
The patent extracts the dielectric material from airgap regions to eliminate the source of TDDB failures. By removing the dielectric in specific areas where unrelated metals are present, the harmful interaction between via bottom and unrelated metal is prevented, thus improving reliability.
2Manufacturing precision
If additional airgap masks are used to form airgaps, then airgap formation precision is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the airgap formation process with the existing dual-damascene via formation process. The same lithographic patterns and etch steps used for via alignment are simultaneously used to define airgap regions, eliminating the need for separate airgap masks and reducing overall process complexity.
Solution Approach 2:
The patent makes the dielectric layer serve multiple functions: it acts as both the alignment reference for via formation and the material to be removed for airgap creation. This multi-functionality allows a single process flow to achieve both precise via alignment and accurate airgap formation without additional masks.
3Loss of energy
If dielectric regions are selectively removed to form airgaps, then capacitance reduction is achieved, but ILD damage and manufacturing difficulty increase
Solution Approach 1:
The patent performs preliminary patterning of the dielectric layer during the via formation process, defining both via locations and airgap regions simultaneously. This preliminary action prepares the structure for subsequent airgap formation while minimizing unintended ILD damage by establishing precise boundaries before removal operations.
Solution Approach 2:
The patent uses the hard mask layer as an intermediary to protect non-airgap regions during dielectric removal. The hard mask serves as a protective barrier that prevents ILD damage in areas where via formation is desired, while allowing controlled removal in airgap regions where the mask is absent or selectively removed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces capacitance and enhances the thermal conductance and mechanical stability of semiconductor devices by integrating airgaps and FAVs at the same metallization level, addressing the reliability issues associated with current processes.
Implementation Method 1
depositing a conformal cap within the recesses, and depositing a dielectric layer such that the airgaps are formed in the airgap regions between the plurality of trenches
Data Source
AI summary
A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.