Fully Aligned Via Interconnect Using Subtractive Patterning
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Solution Overview
Problem
The dual damascene process for forming interconnect structures often results in void formation and increased contact resistance due to the presence of voids and barrier layers in vias, especially as feature sizes are scaled.
Innovation Solution
A fully aligned via interconnect structure is formed using subtractive metal patterning, where vias are self-aligned between metal lines with a stepped profile or sidewall spacers, and a metal film is selectively grown in pockets to align vias accurately, avoiding voids and barrier layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual damascene process is used to form vias, then via formation is achieved, but voids form and contact resistance increases
Solution Approach 1:
The patent removes the barrier layer from the via structure entirely, extracting the harmful element that causes high contact resistance. The via is formed directly in the dielectric without a barrier layer, and metal is deposited directly into the via, eliminating the source of the problem rather than trying to work around it.
Solution Approach 2:
Instead of the conventional approach of building up structure (forming barrier layer then filling metal), the patent inverts the sequence by removing the barrier layer completely and using a different deposition approach. The via is etched, then metal is deposited using atomic layer deposition (ALD) which conformally coats the via walls and bottom without requiring a pre-formed barrier layer.
2Area of moving object
If feature sizes are scaled down, then interconnect density is improved, but void formation increases
Solution Approach 1:
The patent changes the deposition parameters by using atomic layer deposition (ALD) instead of conventional electroplating or CVD. ALD provides superior conformal coverage and better control over film thickness at the nanoscale, which is critical for small feature sizes. The process parameters include controlling deposition temperature, precursor flow rates, and cycle times to achieve void-free filling in scaled features.
3Ease of manufacture
If barrier layer is present at via bottom, then via formation is completed, but contact resistance increases
Solution Approach 1:
The patent removes the barrier layer from the via structure entirely, extracting the harmful element that causes high contact resistance. The via is formed directly in the dielectric without a barrier layer, and metal is deposited directly into the via, eliminating the source of the problem rather than trying to work around it.
Solution Approach 2:
The patent introduces a different material or process as an intermediary between the dielectric and metal. Instead of using a barrier layer, the process uses a specially prepared via interface with controlled surface properties, possibly using a thin adhesion promoter layer or surface treatment that enables direct metal deposition without a traditional barrier layer, thus maintaining both manufacturability and low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance by eliminating voids and barrier layers, enhancing the reliability and efficiency of interconnect structures, particularly at smaller feature sizes.
Implementation Method 1
forming by subtractive etch metal lines Mx−1 and at least one via Vx−1 self-aligned to at least one of the metal lines Mx−1
Implementation Method 2
depositing a metal layer onto the ILD over the at least one via Vx−1
Implementation Method 3
An overetch can be used during the patterning of the metal layer to etch the at least one via Vx−1 self-aligning the at least one via Vx−1 to at least one of the metal lines Mx
Implementation Method 4
Residual metal can be removed using an isotropic etch which forms pockets in the at least one via Vx−1 and the metal lines Mx below the sidewall spacers
Implementation Method 5
a metal film can be selectively grown in the pockets and along a sidewall of the at least one via Vx−1
Data Source
AI summary
A fully aligned via interconnect structure and techniques for formation thereof using subtractive metal patterning are provided. In one aspect, an interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; and at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx, wherein a top surface of at least one of the metal lines Mx−1 has a stepped profile. In another aspect, another interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx; and sidewall spacers alongside the metal lines Mx. A method of forming an interconnect structure is also provided.