Aligning Marks for FinFET Sidewall Image Transfer Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current fabrication processes for FinFETs face challenges such as misalignment issues due to the miniaturization of semiconductor devices, particularly in the sidewall image transfer (SIT) process, which complicates the formation of finer critical dimension fin structures.
Innovation Solution
A semiconductor structure with novel aligning marks is introduced, comprising a mirror symmetrical pattern in the dicing region, including second and third patterns formed through a series of patterned layers and etching processes, specifically designed to facilitate precise alignment during the SIT process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of field effect transistors is continuously shrunk to achieve miniaturization, then device density and integration are improved, but misalignment problems occur and manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary action by forming alignment marks at the dicing region before the main patterning processes. These pre-formed marks serve as reference features for subsequent alignment operations, ensuring that even as device dimensions shrink, the alignment precision is maintained through pre-established reference points that guide the patterning of finer structures.
Solution Approach 2:
The alignment marks act as an intermediary element between the dicing structure and the fin structures. These marks provide a mediating reference system that enables precise alignment during pattern transfer processes, allowing the system to maintain manufacturing precision despite continuous miniaturization of the active device areas.
2Manufacturing precision
If pattern transfer technique such as sidewall image transfer process is used to form finer critical dimension fin structures, then manufacturing precision is improved, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent segments the alignment mark structure into multiple distinct components: a dicing line, first alignment marks on opposite sides of the dicing line, and second alignment marks. This segmentation allows each component to serve specific alignment functions independently, simplifying the overall alignment process while maintaining high critical dimension precision through the coordinated use of these segmented reference features.
Solution Approach 2:
The alignment marks are formed in advance through preliminary patterning steps before the main fin structure formation. This preliminary action creates ready-to-use reference features that guide subsequent pattern transfer processes, reducing the complexity of alignment operations during critical dimension fabrication while ensuring high precision through pre-established geometric references.
3Device complexity
If regular photolithography and etching process are used to form fin structures, then fabrication process simplicity is maintained, but misalignment problems occur due to sub-lithographic requirements
Solution Approach 1:
The alignment marks serve as an intermediary reference system that bridges the gap between simple photolithography processes and the need for sub-lithographic precision. By providing pre-formed geometric references at the dicing region, these marks enable regular photolithography to achieve higher alignment precision than would otherwise be possible, maintaining process simplicity while improving manufacturing precision through the mediating alignment features.
Data Source
AI summary
The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.