Configurable Interface Alignment Buffer for DRAM-Logic Image Sensors
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Solution Overview
Problem
Photosensor arrays with bond-per-pixel-block stacked-wafer designs face challenges in data order, where physically adjacent pixels are not read together due to sequential reading through ADCs, disrupting the natural pixel order, which affects autofocus and edge detection processes that rely on pixel-order sequences.
Innovation Solution
An image sensor with multiple pixel blocks coupled to separate ADCs, where digitized data is fed into an image RAM and then re-ordered by an alignment buffer, using multiport RAM or dual-RAM ping-pong buffers, to ensure adjacent pixels are processed in the correct order by the image processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bond-per-pixel-block stacked-wafer design is used, then manufacturing efficiency and integration are improved, but data output order becomes out-of-sequence preventing adjacent pixels from arriving simultaneously
Solution Approach 1:
The patent introduces an alignment buffer as an intermediary component between the image RAM and the image processor. This buffer receives out-of-order pixel data from the image RAM and reorders it to deliver in-order data to the image processor, thereby resolving the contradiction between the efficient bond-per-pixel-block stacked-wafer design and the requirement for sequential pixel data output for image processing functions.
2Device complexity
If pixels are read sequentially through ADC into image RAM, then data storage is simplified, but physically adjacent pixels do not arrive at image processor together
Solution Approach 1:
The alignment buffer performs preliminary reordering action by receiving pixel data in the order it arrives from the image RAM (which groups pixels by block) and pre-arranging them into the correct sequential order before delivering to the image processor. This preliminary reordering ensures that physically adjacent pixels arrive together at the image processor without complicating the basic sequential read-through-ADC storage mechanism.
3Productivity
If multiport RAM or dual-RAM ping-pong alignment buffer is used, then pixel data reordering efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamic RAM architectures (multiport RAM or dual-RAM ping-pong) for the alignment buffer to achieve efficient pixel data reordering. The dual-RAM ping-pong configuration allows one RAM to be written to while the other is being read from, enabling continuous operation without idle cycles. This dynamic approach improves reordering efficiency while managing complexity through established RAM architectures rather than requiring entirely new structural inventions.
Data Source
AI summary
An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.