Alignment Carrier for Semiconductor Die Interconnect Bridge Assembly
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Solution Overview
Problem
The assembly of semiconductor die using interconnect bridges faces challenges due to mis-registration between low density interconnect (LDI) and high density interconnect (HDI) regions caused by a two-step plating process, making precise alignment and attachment difficult, especially with large pitch controlled collapse chip connections (C4s).
Innovation Solution
An alignment carrier with a substrate having a coefficient of thermal expansion matching that of the interconnect bridge, featuring solder balls of varying sizes for precise alignment and contact with sacrificial bond pads, and a window for accessing the HDI region, allows for the precise alignment and assembly of semiconductor die using an interconnect bridge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a two-step plating process is used to create interconnect bridges, then the interconnect bridge structure can be formed, but mis-registration occurs between LDI and HDI regions leading to alignment difficulties
Solution Approach 1:
The patent introduces an alignment carrier as an intermediary component between the semiconductor die and the final assembly. This carrier includes a substrate with CTE matching the interconnect bridge and features solder balls at periphery regions that contact sacrificial bond pads on the die. The alignment carrier provides a stable reference frame during assembly, mediating the alignment process and eliminating mis-registration issues caused by the two-step plating process.
Solution Approach 2:
The patent changes the thermal expansion parameter by selecting a substrate material whose coefficient of thermal expansion (CTE) substantially matches that of the interconnect bridge. This parameter matching prevents differential thermal expansion during processing, maintaining alignment precision throughout the assembly process and eliminating mis-registration between LDI and HDI regions.
2Ease of operation
If large pitch C4 solder balls are used for alignment, then alignment is simplified, but mis-registration between LDI and HDI regions persists due to two-step plating
Solution Approach 1:
The alignment carrier serves as a mediator that decouples the alignment function from the interconnect bridge structure itself. By providing dedicated alignment features (solder balls on the carrier contacting sacrificial bond pads on the die), the system enables easy alignment operations without compromising the precision of the final HDI registration, as the carrier maintains a stable reference frame throughout the process.
3Adaptability or versatility
If multiple interconnect bridges are assembled, then communication between multiple semiconductor die is enabled, but alignment and attachment difficulty increases significantly
Solution Approach 1:
The alignment carrier is designed as a universal platform that can accommodate multiple semiconductor die with interconnect bridges simultaneously. The carrier's substrate provides a common reference frame, and the array of solder balls at periphery regions enables consistent alignment across multiple die, reducing assembly complexity compared to aligning each bridge individually.
Solution Approach 2:
The patent segments the alignment function from the interconnect bridge function. The alignment carrier handles all alignment operations for multiple die, while the interconnect bridges focus solely on electrical connection. This segmentation allows parallel processing of multiple alignments, reducing overall assembly complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables accurate alignment and assembly of semiconductor die, circumventing mis-registration issues and ensuring proper attachment of interconnect bridges between HDI regions, thereby improving yield and reducing defects.
Implementation Method 1
a substrate having a coefficient of thermal expansion (CTE) that substantially matches that of an interconnect bridge
Data Source
AI summary
An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.