Alignment Circuit for Packet Rearrangement in Receiving Apparatus
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Solution Overview
Problem
Existing packet rearrangement techniques in receiving apparatuses, particularly for TCP/IP communication, face inefficiencies due to assumptions of sequential sequence numbers, leading to incorrect packet placement and frequent CPU interruptions, resulting in poor processing efficiency.
Innovation Solution
An alignment circuit is introduced that includes an alignment buffer and a control circuit to determine the correct placement of packets based on sequence numbers, using methods such as consecutive bit or pointer-based searches to efficiently identify the boundary areas for packet placement, thereby avoiding incorrect assumptions about sequence number increments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If packet rearrangement is performed by CPU, then packet processing can be done flexibly, but CPU burden increases and processing efficiency deteriorates
Solution Approach 1:
The packet rearrangement function is segmented from the CPU and implemented as a dedicated hardware circuit. The alignment circuit includes a buffer memory for storing packet data, a writing unit for writing packets to the buffer, and a reading unit for reading packets from the buffer in sequence order, thereby offloading the rearrangement task from the CPU while maintaining processing flexibility.
Solution Approach 2:
A dedicated alignment circuit acts as an intermediary between the network interface and the CPU. This circuit includes a buffer memory that temporarily stores incoming packets, a writing unit that receives packets from the network, and a reading unit that outputs packets in sequence order to the CPU, thereby mediating the packet rearrangement process without burdening the CPU.
2Productivity
If packet rearrangement is performed by hardware, then processing efficiency improves, but device complexity increases
Solution Approach 1:
The alignment circuit is designed with multi-functionality to handle various packet types and protocols (TCP, UDP, ICMP) through a single unified structure. The buffer memory can store different packet types, and the control logic can adapt to different protocols, thereby improving processing efficiency without proportionally increasing device complexity.
Solution Approach 2:
The alignment circuit uses parameter changes in the form of sequence numbers to control packet rearrangement. By extracting and comparing sequence numbers from packet headers, the circuit dynamically determines the correct output order without requiring complex hardwired logic for each possible packet sequence, thereby achieving efficient rearrangement with moderate circuit complexity.
3Device complexity
If sequence numbers are assumed to be sequential, then packet placement is simplified, but correctness deteriorates when non-sequential numbers occur
Solution Approach 1:
The reading unit continuously monitors the sequence numbers of packets read from the buffer and provides feedback to the writing unit. When a packet with a non-sequential sequence number is detected, the feedback mechanism triggers the writing unit to adjust its placement strategy, thereby maintaining placement correctness while preserving relative simplicity in the overall packet placement process.
Solution Approach 2:
The writing unit performs preliminary actions by pre-processing packet sequence numbers before writing packets to the buffer. It extracts and validates sequence numbers in advance, and when non-sequential numbers are detected, it prepares appropriate placement positions beforehand, thereby ensuring correct packet placement without requiring complex real-time decision-making during packet arrival.
Data Source
AI summary
A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.