Redistribution Layer Alignment Groove Etching for Lithography Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication processes face alignment issues due to deep alignment grooves in redistribution layers, leading to alignment failures in lithography machines due to high depth-to-width ratios, which cause noise and accuracy problems.
Innovation Solution
A method is introduced where a protective layer with a lower etching rate than the isolation material layer is used to form an alignment groove with a depth less than the thickness of the isolation layer, reducing the depth-to-width ratio and minimizing laser light reflections, thereby improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a deep alignment groove is formed in the redistribution layer, then the alignment structure is more prominent and easier to detect, but the depth-to-width ratio increases causing loud noises to alignment of lithography machines and alignment failure
Solution Approach 1:
The patent changes the depth parameter of the alignment groove from deep to shallow (depth less than thickness of isolation layer), and adjusts the width parameter accordingly. This parameter optimization reduces the depth-to-width ratio, eliminating loud noises during lithography machine alignment while maintaining sufficient alignment detection capability through the optimized groove dimensions.
2Illumination intensity
If a deep alignment groove is formed, then the alignment feature is more visible, but the high depth-to-width ratio causes laser light reflections and alignment failure
Solution Approach 1:
By optimizing the depth parameter to be less than the thickness of the isolation layer and adjusting the width parameter, the patent reduces the depth-to-width ratio of the alignment groove. This parameter change minimizes laser light reflections and noise while maintaining sufficient visibility for alignment detection, thereby eliminating alignment failure.
3Manufacturing precision
If a protective layer with lower etching rate is used, then the alignment groove depth is reduced improving alignment accuracy, but the etching process becomes more complex
Solution Approach 1:
The patent introduces a protective layer as an intermediary material between the isolation layer and the etching process. This protective layer with lower etching rate acts as a mediator that enables precise control of the alignment groove depth (less than isolation layer thickness) while simplifying the overall process by preventing over-etching and eliminating the need for complex multi-step etching control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances alignment accuracy by reducing errors in lithography machines and preventing alignment failures, while also improving production efficiency and reducing costs through a one-step etching process.
Implementation Method 1
etching the isolation material layer group and the protective layer, an etching rate of the protective layer being less than an etching rate of the isolation material layer group
Data Source
AI summary
Embodiments provide a semiconductor device and a fabrication method. The fabrication method includes: providing a substrate including an alignment region and a connection region; forming a first conductive layer on the substrate; forming a spacer material layer group on the first conductive layer; forming a protective layer on the spacer material layer group, the protective layer being positioned on the alignment region; etching the spacer material layer group and the protective layer, an etching rate of the protective layer being less than an etching rate of the spacer material layer group to remove the spacer material layer group on the connection region to form a spacer layer group, and forming an alignment groove on the spacer layer group in the alignment region; and forming a second conductive layer group on the spacer layer group and the first conductive layer, the second conductive layer group covering the alignment groove.