Semiconductor Alignment Key Trench Structure
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Solution Overview
Problem
The challenge in fabricating semiconductor devices lies in achieving high accuracy and reliability due to reduced process margins in the exposure process, particularly in forming fine patterns, which is crucial for high-speed and highly integrated semiconductor devices.
Innovation Solution
A semiconductor device design that incorporates an alignment key with a specific trench structure, including a first and second width configuration, and sidewall conductive patterns to enhance alignment and reduce lifting failures during the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional alignment key structure is used, then the alignment process can be performed, but lifting failures occur during fabrication due to insufficient structural support
Solution Approach 1:
The alignment key is divided into multiple sub-alignment key patterns (first sub-alignment key pattern and second sub-alignment key pattern) that are sequentially stacked. This segmentation provides distributed structural support throughout the alignment key depth, preventing lifting failures while maintaining the overall alignment function.
Solution Approach 2:
The alignment key employs a nested structure where multiple conductive patterns and dielectric layers are stacked sequentially, with each layer embedded within the previous one. The first conductive pattern is surrounded by first dielectric, which is surrounded by second dielectric, creating a nested configuration that enhances structural integrity and prevents lifting.
2Productivity
If the exposure process uses fine patterns for high integration, then device integration increases, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The alignment key structure is prepared in advance with multiple pre-formed conductive patterns and dielectric layers before the actual alignment process. This preliminary structuring provides stable reference features for exposure alignment, enabling precise pattern formation even at high integration levels where manufacturing margins are reduced.
3Measurement precision
If a simple alignment key structure is used, then device complexity is reduced, but alignment precision is insufficient for high-speed semiconductor devices
Solution Approach 1:
Different regions of the alignment key are assigned different functional qualities: the first sub-alignment key pattern provides structural support and stability, while the second sub-alignment key pattern provides additional alignment references. The sidewall conductive patterns are specifically positioned to enhance local alignment precision without uniformly increasing complexity throughout the entire structure.
Data Source
AI summary
A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.