Semiconductor Alignment Mark Structure After CMP Planarization

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Solution Overview

Problem

During semiconductor fabrication, the CMP planarization process often flattens alignment marks on previous layers, making them unreadable for subsequent metallization layers, leading to potential mask misalignment issues and fabrication flaws.

Innovation Solution

A semiconductor structure with a clear alignment mark formed after planarization, using an alignment mark layer with trenches that remain observable after metallization, ensuring accurate alignment for subsequent layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If CMP planarization process is performed to flatten the wafer surface, then surface flatness is improved, but alignment marks on previous layers are flattened and become unreadable

Engineering Contradiction:

Improvesurface flatnessVSAvoidalignment mark readability

Core Design Contradiction:

ShapeVSLoss of information

Solution Approach 1:

The patent forms a new alignment mark layer on the planarized surface before subsequent metallization processes. This preliminary action ensures that fresh, readable alignment marks are available on the current layer, compensating for the loss of visibility of underlying layer marks due to CMP flattening.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent transitions from relying on alignment marks from previous layers (vertical dimension/depth) to creating alignment marks on the current planarized layer (horizontal dimension/surface). This dimensional shift ensures alignment functionality is maintained despite the CMP process affecting previous layer features.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If photolithographic mask alignment precision is increased, then layer alignment accuracy is improved, but fabrication process complexity increases

Engineering Contradiction:

Improvelayer alignment accuracyVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent creates alignment marks that are self-generated on each layer through the alignment mark layer formation process. These self-service alignment marks eliminate the need for complex external alignment systems, achieving high precision while simplifying the overall fabrication process.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent changes the approach from physical mask alignment to optical detection of alignment marks. By forming distinct alignment mark features with specific geometric parameters (trenches, bridges, etc.), the system achieves precise alignment through optical detection rather than mechanical mask positioning, reducing process complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11901305B2Method for fabricating semiconductor structure having alignment mark feature

Publication Date: 2024.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.