Alignment Mark with Dummy Pattern for Overlay Precision

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Solution Overview

Problem

Current overlay measurement methods in semiconductor manufacturing often result in overlay errors due to measurement deviations, leading to inaccuracies in the relative positioning of successive layers during photolithographic processes.

Innovation Solution

The introduction of a dummy alignment mark pattern in the blank region, with smaller dummy mark units covered by larger mark units in the alignment mark, reduces the dishing phenomenon during planarization, thereby improving the accuracy of alignment by adding dummy alignment marks in the blank region to prevent recessing and enhance measurement precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If overlay measurement is performed using conventional alignment marks, then measurement can be completed, but measurement precision is reduced due to dishing phenomenon in blank regions

Engineering Contradiction:
Improveoverlay measurement accuracyVSAvoiddishing phenomenon
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming dummy alignment marks in the blank region before the actual measurement process. These dummy marks are created during the same photolithographic process as the alignment marks, ensuring that the blank region has sufficient material coverage before planarization. This preliminary placement of material prevents the dishing phenomenon from occurring during subsequent CMP processes, thereby maintaining measurement precision without requiring post-process corrections

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If dummy alignment marks are added in blank region, then dishing phenomenon is reduced, but device complexity increases

Engineering Contradiction:
Improvealignment accuracyVSAvoidalignment mark structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the dummy alignment marks to serve multiple functions simultaneously. The dummy marks in the blank region not only prevent dishing phenomenon during planarization but also maintain the same structural characteristics as the actual alignment marks, allowing them to be processed through the same photolithographic and CMP steps. This multi-functionality reduces the need for separate process steps or specialized structures, thereby limiting the increase in manufacturing complexity while achieving improved alignment accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10566290B2Alignment mark and measurement method thereof
Publication Date: 2020.02.18 UNITED MICROELECTRONICS CORP
  • US10566290B2 patent drawing
  • US10566290B2 patent drawing
  • US10566290B2 patent drawing

AI summary

The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.