Alignment Mark Layout With Dummy Pattern for Optical Contrast
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Solution Overview
Problem
The presence of circuit layers underneath alignment mark patterns in semiconductor devices reduces the optical contrast between the alignment region and the alignment mark, leading to alignment errors and inefficient use of space due to required circuit clearance regions.
Innovation Solution
Incorporating a dummy pattern electrically insulated from the lower electrical pattern, which overlaps the alignment mark pattern and provides an optical contrast greater than 50, allowing the alignment mark to be recognized by a camera while enabling interconnect circuits to overlap the dummy pattern without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If circuit layers are placed underneath the alignment mark pattern, then space usage efficiency is improved, but optical contrast between the alignment region and alignment mark is reduced
Solution Approach 1:
The patent divides the area underneath the alignment mark pattern into two functional zones: a first area containing circuit layers and a second area containing a dummy pattern. This segmentation allows circuit layers to occupy space while maintaining optical contrast by placing the dummy pattern in the region directly beneath the alignment mark where high contrast is needed for optical recognition.
Solution Approach 2:
The dummy pattern acts as an intermediary element between the circuit layers and the alignment mark pattern. It provides the necessary optical contrast for alignment recognition while allowing circuit layers to be positioned in the surrounding first area, thus mediating between the conflicting requirements of space utilization and optical contrast.
2Manufacturing precision
If a circuit clearance region is created extending from the alignment region to the substrate, then alignment accuracy is improved, but space usage efficiency deteriorates
Solution Approach 1:
The patent segments the traditional circuit clearance region into two distinct areas: a first area for circuit routing and a second area containing the dummy pattern. This segmentation eliminates the need for an extended clearance region by concentrating the optical contrast-providing function in the second area directly beneath the alignment mark, allowing circuits to efficiently utilize the first area without compromising alignment accuracy.
3Adaptability or versatility
If interconnect circuits are routed underneath the alignment mark pattern, then routing flexibility is improved, but optical contrast is reduced
Solution Approach 1:
The patent segments the space underneath the alignment mark pattern into a first area for interconnect circuit routing and a second area for the dummy pattern. This segmentation enables interconnect circuits to pass through the first area with high routing flexibility while the dummy pattern in the second area maintains the necessary optical contrast for alignment mark recognition.
Data Source
AI summary
A semiconductor device includes a substrate, an upper layer disposed over the substrate and comprises an upper electrical pattern and an alignment mark pattern electrically insulated from the upper electrical pattern, and a lower layer disposed between the substrate and the upper layer and including a lower electrical pattern and a dummy pattern electrically insulated from the lower electrical pattern, wherein the alignment mark pattern overlaps the dummy pattern from a top view, the alignment mark pattern has an optical contrast in relation to the dummy pattern, and the optical contrast is substantially equal to or greater than 50.