Alignment Mark Protection in Semiconductor Etching
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Solution Overview
Problem
The alignment mark in semiconductor manufacturing processes is easily etched away during repeated etching steps, leading to alignment issues in subsequent photo engraving processes due to its thin membrane in non-display regions.
Innovation Solution
A method involving the formation of a gate and alignment mark coplanarly on a transparent substrate, with a gate insulation layer covering both, followed by the creation of an oxide semiconductor layer and an etching stop layer to protect the alignment mark from etching, ensuring its retention throughout the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the alignment mark is formed with a thin membrane in the non-display region during the first photo engraving process, then the photo mask can precisely form the required stack structure by aligning the alignment mark, but the alignment mark is easily etched away during repeated etching steps
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the alignment mark before the etching process begins. This protective layer is deposited in advance to shield the alignment mark from subsequent etching steps, ensuring the alignment mark remains intact throughout the manufacturing process while maintaining its alignment functionality
Solution Approach 2:
The protective layer serves as an intermediary element between the etching process and the alignment mark. This intermediate layer allows the etching process to proceed while preventing direct contact between the etchant and the alignment mark, thus preserving the alignment mark's integrity without interfering with the overall manufacturing process
2Ease of manufacture
If repeated etching steps are performed to form the required stack structure, then the gate, drain, source, and channel are successfully formed, but the alignment mark is etched away due to its thin membrane
Solution Approach 1:
The protective layer acts as an intermediary that allows repeated etching steps to be performed on the stack structure while preventing etching damage to the alignment mark. The etching process can proceed through the protective layer to form the required stack structure, and the protective layer can be removed afterward, leaving the alignment mark intact
Solution Approach 2:
The protective layer provides preliminary anti-action by preemptively protecting the alignment mark from etching damage before the harmful etching process occurs. This counter-measure is established in advance to neutralize the potential harm that would otherwise be inflicted on the alignment mark during the necessary etching steps
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.