Semiconductor Alignment Mark Frame Layout for Lower Overlay Error
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Solution Overview
Problem
In the fabrication of microcircuit devices, precise alignment of photolithographic masks with the semiconductor wafer is challenging due to increasing device density and smaller feature sizes, leading to overlay errors and misalignment issues, which can result in defective wafers and reduced performance.
Innovation Solution
The use of an alignment region with a frame bordering the alignment mark, which includes multiple frames and alignment marks, helps reduce photoresist loading and improves alignment procedures by providing additional alignment references, enhancing critical dimension stability and optical proximity correction effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If photolithographic masks are aligned with the semiconductor wafer during the masking step, then alignment accuracy is improved, but overlay errors and misalignment issues still occur due to increasing device density and smaller feature sizes
Solution Approach 1:
The patent introduces an alignment region with alignment marks as an intermediary element between the photolithographic mask and the semiconductor wafer. This alignment region serves as a mediator that facilitates precise alignment by providing reference marks that can be detected and used to adjust the mask position, thereby reducing overlay errors caused by increasing device density and smaller feature sizes.
Solution Approach 2:
The patent creates a copy of the alignment structure by forming an alignment region with alignment marks that replicate the pattern structure. This copied alignment region is specifically designed to work with the photolithographic process, allowing the mask to be aligned accurately by referencing the copied pattern in the alignment region, thus improving alignment accuracy while accounting for smaller feature sizes.
2Measurement precision
If alignment regions with frames bordering alignment marks are used, then alignment accuracy is improved, but photoresist loading increases
Solution Approach 1:
The patent applies local quality by creating a frame structure with specific properties around the alignment marks. The frame has different characteristics from the surrounding areas, providing enhanced alignment reference while being localized to specific regions. This localized enhancement improves alignment accuracy without requiring photoresist loading across the entire wafer, thus managing the trade-off between alignment precision and photoresist consumption.
Data Source
AI summary
According to some embodiments of the disclosure, a semiconductor structure includes a first alignment region defined in a substrate layer and a first frame at edges of the first alignment region. A first alignment mark is in the first alignment region and bordered by the first frame. According to some embodiments of the disclosure, a method of fabricating a semiconductor structure includes forming an isolation structure over a substrate layer in a first alignment region. A process layer is formed over the isolation structure. A patterned mask is formed over the process layer. The process layer is patterned using the patterned mask as a template to form a first frame at edges of the first alignment region and a first alignment mark in the first alignment region and bordered by the first frame.