Alignment Mark Integration with Guard Ring in Semiconductor Substrates
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Solution Overview
Problem
The existing semiconductor chip manufacturing processes face challenges such as alignment marks being cut during dicing, leading to defects, reduced adhesiveness, and potential shorts between bonding pads, which hinders miniaturization and increases the risk of cracks in protective films, affecting the reliability and yield of semiconductor chips.
Innovation Solution
A semiconductor apparatus is designed with alignment marks that contact or are spaced from a protective wall and covered by a protective film, preventing them from being cut during dicing and reducing the risk of cracks, while allowing for miniaturization by not occupying chip area, thus enhancing the reliability and yield of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment marks are formed over scribe lines, then alignment marks are available for laser trimming and overlay, but alignment marks are cut during dicing causing peeling, curling, and shorts between bonding pads
Solution Approach 1:
The alignment marks are extracted from the scribe line area and relocated to the chip area, specifically positioned within the guard ring structure. This extraction prevents the alignment marks from being cut during dicing while maintaining their alignment functionality for laser trimming and overlay processes.
Solution Approach 2:
The alignment marks are merged with the guard ring structure, where the alignment marks are formed as integral parts of the guard ring pattern. This merging allows the alignment marks to be protected by the guard ring's continuous structure during dicing while serving dual purposes of protection and alignment.
2Reliability
If protective film is formed over scribe line area, then integrated circuits are protected from moisture and sediment, but protective film is cut during dicing causing cracks that break guard rings
Solution Approach 1:
The protective film formation is extracted from the scribe line area and limited to only the chip area. By defining the protective film's coverage boundary to exclude the scribe line region, the film avoids being cut during dicing, preventing crack formation and subsequent guard ring failure while still providing moisture protection to the integrated circuits.
3Reliability
If alignment marks are formed in semiconductor chip, then alignment marks are not cut during dicing, but chip area is reduced due to alignment mark occupation
Solution Approach 1:
The alignment marks are merged with the guard ring structure, where the alignment mark pattern is formed as part of the guard ring's continuous wiring pattern. This merging allows the alignment marks to be positioned within the guard ring's perimeter, utilizing the guard ring's area efficiently and minimizing additional chip area consumption while ensuring the alignment marks remain intact during dicing.
4Reliability
If guard rings are formed with slits or vias to disperse stress, then crack propagation is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of introducing slits or vias into the guard ring to disperse stress, the invention inverts the approach by making the guard ring continuous and unbroken. The alignment marks are positioned within the guard ring's continuous structure, allowing the guard ring to maintain its integrity and provide uniform stress distribution without requiring additional complex features like slits or vias.
Data Source
AI summary
A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.