Alignment Mark Height for Flip Chip Underfill Visibility

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Solution Overview

Problem

In flip chip mounting, the low optical transparency of underfill resin makes it difficult to accurately align alignment marks, leading to potential connection errors such as shorts between solder bumps.

Innovation Solution

The alignment marks are formed with a height greater than the connection electrodes, allowing them to be easily recognizable even after the underfill resin is applied, using a method that includes forming a barrier layer, resist patterns, and electrolytic plating to create the marks and connection electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If underfill resin is applied to cover connection electrodes, then reliability of the assembly is improved, but optical transparency is reduced making alignment marks difficult to identify

Engineering Contradiction:
Improveassembly reliabilityVSAvoidalignment mark visibility
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The alignment mark is extended in the vertical dimension (height) to protrude above the underfill resin surface. This dimensional change allows the alignment mark to be visible through the translucent underfill resin, solving the visibility problem while maintaining the protective function of the underfill resin.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The alignment mark is formed with a material having different optical properties (higher refractive index) than the underfill resin, creating contrast that enhances visibility. The material composition is specifically chosen to provide optical contrast against the underfill resin background.

Inventive Principle:
Principle #32Color changes

2Ease of manufacture

If alignment marks are formed at the same height as connection electrodes, then manufacturing process is simplified, but accurate alignment cannot be achieved through underfill resin

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidalignment accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The alignment mark is given a greater height than the connection electrode, creating a vertical dimension difference that allows the mark to protrude through the underfill resin. This enables visual alignment verification while maintaining a relatively simple two-step plating process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Difficulty of detecting and measuring

If alignment mark height is increased above connection electrode, then alignment mark visibility through underfill resin is improved, but device complexity increases

Engineering Contradiction:
Improvealignment mark visibilityVSAvoidstructure complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The alignment mark and connection electrode are formed in an integrated manufacturing process using sequential plating steps. The alignment mark structure is combined with the existing electrode formation process, avoiding the need for separate alignment mark fabrication steps and reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables accurate positional alignment and reduces connection errors by ensuring the alignment marks can be identified through the underfill resin, enhancing the reliability of the semiconductor device assembly.

Implementation Method 1

forming a barrier layer on the wafer

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

forming the alignment mark in the opening portion of the first resist pattern by using an electrolytic plating method

Methodology Applied
Scientific EffectElectrolytic plating: Electroplating

Data Source

PatentUS9202804B2Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2015.12.01 SONY GROUP CORP
  • US9202804B2 patent drawing
  • US9202804B2 patent drawing
  • US9202804B2 patent drawing

AI summary

A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.