Semiconductor Alignment Mark Hollow Pattern

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor devices require a reserved region for alignment marks, limiting circuit layout and increasing costs due to unused space.

Innovation Solution

Incorporating hollow patterns in alignment marks on the semiconductor device's substrate, allowing traces to pass through and enhancing identification rates by creating sharper optical variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a reserved region is allocated for the alignment mark in conventional semiconductor devices, then the alignment mark can be properly positioned, but the circuit layout is limited and the device cost increases due to unused space

Engineering Contradiction:
Improvealignment mark identification rateVSAvoidusable circuit region
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The alignment mark incorporates hollow patterns (porous structure) that allow light to pass through, creating sharper optical variations for better identification. The hollow patterns consist of multiple sub hollow patterns with spaces that enhance optical contrast while allowing the region to be reused for circuit traces

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The region containing the alignment mark serves dual purposes: it maintains alignment functionality while also being usable for circuit traces. The hollow patterns enable the alignment mark to be identified optically while allowing trace signals to pass through the same region, eliminating the need for dedicated reserved space

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If a reserved region is allocated for the alignment mark, then proper alignment is achieved, but the device cost increases due to reduced effective area

Engineering Contradiction:
Improvealignment mark identification rateVSAvoiddevice cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The alignment mark region is merged with the circuit region, allowing both alignment functionality and circuit functionality to coexist in the same physical space. The hollow patterns enable this merging by providing optical contrast for alignment while allowing electrical traces to be routed through the same area

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hollow patterns create a porous structure in the alignment mark that allows optical penetration for identification while permitting the region to be reused for circuit traces, thereby reducing the total device area required and lowering manufacturing costs

Inventive Principle:
Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The hollow patterns improve alignment mark identification rates, enabling the use of reserved regions for circuit traces and reducing semiconductor device costs.

Implementation Method 1

the hollow pattern causes the optical variation of the alignment mark is sharper

Methodology Applied
Scientific EffectOptical variation: Reflection

Data Source

PatentUS8912671B2Semiconductor device having alignment mark
Publication Date: 2014.12.16 HIMAX TECH LTD
  • US8912671B2 patent drawing
  • US8912671B2 patent drawing
  • US8912671B2 patent drawing

AI summary

A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.