Alignment Mark Formation via Isolation Layer and TSV
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Solution Overview
Problem
In semiconductor processing, misalignment of layers during photolithography techniques can lead to operational failures in devices, highlighting the need for precise alignment marks to ensure the integrity and functionality of semiconductor structures.
Innovation Solution
A method involving the formation of a substrate with through substrate vias (TSVs) and an isolation layer with a recess, where a conductive material is placed within the recess, forming alignment marks that prevent metal diffusion and improve alignment precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography techniques are used for layer formation, then device structure can be created, but alignment precision between layers deteriorates leading to device failure
Solution Approach 1:
Alignment marks are introduced as intermediary structures between the substrate and subsequent photolithography layers. These marks serve as reference features that mediate the alignment process, allowing the stepper to accurately position each layer relative to previous layers, thereby resolving the alignment precision issue without compromising device integrity
Solution Approach 2:
The patent replaces manual or mechanical alignment methods with automated optical alignment systems. The stepper uses optical detection of alignment marks to automatically adjust wafer positioning, substituting mechanical alignment procedures with optical-field-based precision positioning that achieves sub-micron alignment accuracy
2Manufacturing precision
If alignment marks are formed using conventional methods, then alignment precision improves, but metal diffusion occurs compromising structure integrity
Solution Approach 1:
An isolation layer is introduced as an intermediary barrier between the alignment mark conductor and the substrate. This isolation layer prevents direct contact and potential metal diffusion while still allowing the alignment mark to fulfill its alignment function, thus eliminating the harmful metal diffusion effect
Solution Approach 2:
The harmful metal diffusion pathway is extracted or removed from the system by introducing the isolation layer. The conductor is taken out from direct contact with the substrate and placed within an isolated environment, preventing the diffusion of metal atoms into the substrate that would compromise device integrity
3Productivity
If substrate thickness is reduced to enable stacking, then device integration increases, but stress in substrate increases leading to potential failure
Solution Approach 1:
The isolation layer serves as a cushioning or stress-absorbing layer between the conductor and the thinned substrate. This pre-positioned structural element absorbs and distributes mechanical stress that would otherwise concentrate in the thinned substrate, preventing stress-induced failures while enabling the substrate thinning required for stacking
Solution Approach 2:
The patent creates a composite structure consisting of the substrate, isolation layer, and conductor. This composite construction combines materials with different mechanical properties to achieve both thin substrate thickness for stacking and adequate stress resistance, as the isolation layer provides mechanical support and stress distribution
Data Source
AI summary
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.